This video is part of TechXchange: RISC-V: The Instruction-Set Alternative and TechXchange Talks
RISC-V International has released a number of new specifications that enhance the RISC-V ecosystems. I talked with Chief Technology Officer for RISC-V International, Mark Himelstein, about their latest specifications. This includes E-Trace, the Supervisor Binary Interface (SBI) specification, and the UEFI specification.
Himelstein also discusses the RISC-V Zmmul extension. He noted, "Zmmul was very interesting because it was targeted by the embedded folks. They championed it. Our original multiplier also had divide with it and it had multiply and divide. They said, 'we don't want to use too much chip space.'" The Zmmul provides multiplication support without the divide overhead. This doesn't change the instruction set; it only defines an implementation that doesn't include the divide support, only the multiply.
The E-Trace specification defines a standard mechanism for accessing trace information from a RISC-V platform. Like the RISC-V ISA, the specification defines the interface rather than the implementation, allowing the designer to optimize a particular implementation. It defines details like the communication packet (see figure).
The SBI specification defines the interface between the Supervisor Execution Environment (SEE) and the supervisor. The supervisor can execute privileged operations by using the ecall instruction. "Examples of SEE and supervisor are M-Mode and S-Mode on Unix-class platforms, where SBI is the only interface between them, as well as the Hypervisor extended-Supervisor (HS) and Virtualized Supervisor (VS)." A number of members have already implemented SBI support.
The Unified Extensible Firmware Interface Forum (UEFI.org) defines a cross-platform firmware interface that's used on modern x86 and Arm platforms. The latest announcement from RISC-V International adds the RISC-V platform to the mix.
