RISC-V-Based Open-Source Cores Have Processor Subsystem IP, Tools

Check out our embedded world 2023 coverage. This video also is part of TechXchange: RISC-V: The Instruction Set Alternative.

At embedded world 2023, OpenHW Group showcased its CORE-V Family of Open Source RISC-V Cores for High Volume Production SoCs, a series of RISC-V based open-source cores with associated processor subsystem IP, tools, and software. Able to facilitate rapid design innovation and ensure effective manufacturability of production SoCs, CORE-V cores are verified with CORE-V-VERIF, an industrial-grade functional verification platform. It leverages verification components developed by the RISC-V community.

In this video, Low Power Futures' Abdoulaye Berthe discusses a compact and complete security engine that enables efficient computation of operations such as encryption, hash function, and elliptic-curve scalar-to-point multiplication. Timing and side-channel attack resistant, it has an AMBA Standard Interface and a FPGA validation platform as well as a complete UVM Verification Environment. The LP-SEC-ENG offers low-power security in a cost-effective manner by providing support for both ECDHE (elliptic-curve Diffie-Hellman ephemeral) and ECDSA (elliptic-curve digital signature algorithm) approaches.

Related links:

• OpenHW Group
• Low Power Futures
• Low Power Security Engine
• More embedded world 2023 coverage