Integration of the direct link ECC protocol in the memory.
Addressing demanding applications such as advanced driver-assistance systems (ADAS) and in-vehicle infotainment, Micron’sLPDDR5X offers enhanced error correction to increase bandwidth and performance. Its optimized error-correction-code (ECC) scheme mitigates all system in-line ECC penalties, enabling a 15% to 25% bandwidth increase.
Called the direct link ECC protocol (DLEP), the LPDDR5X-optimized ECC scheme not only boosts performance, but it also helps achieve the ISO 26262 ASIL D hardware metric through reduced failures in time (FIT). Furthermore, it delivers approximately 10% lower power consumption on a pJ/b (picojoule-per-bit) perspective and a minimum 6% additional addressable memory space.
The LPDDR5X DRAM with DLEP is JEDEC-compatible, offers a product lifecycle of over five years, and can operate at extreme temperature ranges. Providing the increased bandwidth required by high-performance applications, DLEP-enabled LPDDR5X DRAM is an example of solutions that solve memory and storage challenges for the automotive market.
An Army veteran, Alix Paultre was a signals intelligence soldier on the East/West German border in the early ‘80s, and eventually wound up helping launch and run a publication on consumer electronics for the US military stationed in Europe. Alix first began in this industry in 1998 at Electronic Products magazine, and since then has worked for a variety of publications in the embedded electronic engineering space. Alix currently lives in Wiesbaden, Germany.
Also check out his YouTube watch-collecting channel, Talking Timepieces.
