OC-3 FEC Chip Reduces Required Bandwidth

Nov. 1, 2000
Based on the company's enhanced Turbo Product Code (eTPC) technology, the Astro OC-3 forward error correction (FEC) chip claims to give designers the power to decide what combination and level of benefits work best for their application. The device is

Based on the company's enhanced Turbo Product Code (eTPC) technology, the Astro OC-3 forward error correction (FEC) chip claims to give designers the power to decide what combination and level of benefits work best for their application. The device is also said to be able to do any one of the following: reduce required bandwidth by two times; increase data throughput by two times; increase range by 40%; reduce antenna size by 30%; reduce transmitter power by 2X; or reduce the required noise figure of the receiver by 3 dB. The IC is designed for use in satellite communications, wireless LANs, wireless digital broadcast systems, and more. It provides up to 3 dB of coding gain and achieves channel rates of 200 Mb/s. The Astro OC-3 prototype is available now with volume shipping in Q1 2001. Price is $100 each/1,000.

Company: ADVANCED HARDWARE ARCHITECTURES

Product URL: Click here for more information

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!