Digital ICs/DSP: Chip Set Simplifies HDTV And Set-Top-Box Design

Feb. 2, 2004

The high-definition television (HDTV) and set-top-box (STB) markets have a new high-performance two-chip set at their disposal. The S5H2010 MPEG-2 decoder and S3C2800 digital TV CPU offer a cost-competitive solution, enabling consumer electronics manufacturers to push the wide adoption of HDTVs and HD STBs. The chip set packs a 200-MHz ARM9 32-bit RISC processor core, single HD-capable MPEG-2 decoder, transport demultiplexer, 2D graphic engine, display processor engine, NTSC/PAL encoder, and smart-card and PCI interfaces. To simplify design and speed time-to-market, a development platform and reference design kit supply production-ready middleware, device drivers, application software, and local technical support. The initial platform is built on pSOS and Linux embedded operating systems. The S5H2010/S3C2800 chip-set solution is available now in production quantities.

Samsung Electronics Co. Ltd.www.usa.samsungsemi.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.