Dual-Edge PWM Improves Multiphase Regulators

July 1, 2007
Active pulse positioning leverages conventional PWM techniques and independent phase-current control to reduce the output capacitance required in multiphase voltage regulators.

Transient response is a key performance parameter for the multiphase voltage regulator, especially in microprocessor applications. Conventional pulse-width modulation (PWM) schemes have delay times that can increase the demand on the output capacitors, forcing designs to employ more capacitors for acceptable performance.

A new PWM scheme called active pulse positioning (APP) achieves very fast transient response by dramatically reducing the modulator delay time. This modulation scheme adopts two separate ramp signals to control both the leading edge and trailing edge of the PWM pulse. Controller ICs that implement APP modulation can respond to transient events immediately and require much less output capacitance than other modulators.

Regulating Dynamic Loads

With fast transient response, less output capacitance is needed to meet the design specifications for the regulator. For most applications, the output voltage will drop to its minimum value in several switching cycles after the step load is applied and then settle to its final value slowly. For these applications, increasing the closed-loop bandwidth is important for fast transient response.

This situation is compounded for multiphase voltage regulators for microprocessor core power applications. The current drawn by modern microprocessors is highly dynamic with a wide-varying transient duration and repetition rate. The typical step-load current can be as high as 100 A with a slew rate up to 1000 A/µs. To address this demand, the voltage regulator needs its output voltage to settle rapidly after the transient event in order to be ready for the next transient event.

Adaptive voltage positioning (AVP) control, also referred to as droop control or load-line control, is a popular scheme used to power today's microprocessors. With this control, the output voltage will be reduced in proportion to the load current; the output voltage at heavy load is lower than that at light load, resulting in more cost-effective transient-load regulation. The output voltage after the step load does not need to return to its original value, resulting in much shorter settling time.

The typical response and settling time for the voltage regulator with AVP control is only a few microseconds in typical microprocessor core regulators. With a typical 300-kHz switching frequency, this means the transient event can occur and the regulator must respond completely within one switching cycle. Therefore, any delay in the system will have significant impact on the transient response, and the conventional loop bandwidth concept is not adequate for analyzing the regulator performance. Instead, it is necessary to investigate and reduce the delays in the entire system to improve the transient performance.

Limitations of Conventional PWM

Fig. 1 shows the output stage of a typical 4-phase voltage regulator. Assuming that the high-voltage spike caused by the bulk-capacitor equivalent series inductance (ESL) is absorbed by the high-frequency ceramic capacitors, the capacitor equivalent series resistance (ESR) and the inductor current slew rate become the main factors that impact the transient performance. When the load step is applied to the voltage regulator, the output voltage will drop immediately and the initial voltage drop depends on the ESR of the output capacitor. AVP control will regulate the output voltage to the new value based on the output current.

During the settling time, the output capacitor is discharged to provide some portions of the load current, while the inductor current increases in response to the larger load current. When the inductor current slew rate matches that of the discharging current from the output capacitor, the output voltage waveform can approach an ideal square wave, if desired. Thus, with an increase to the total inductor current slew rate, the current demand on the output capacitors will be reduced and less output capacitance will be required.

There are two parameters that determine the time for the total inductor current to ramp up to the load current: the delay time of the PWM pulses and the slew rate of the total inductor current. To reduce the delay of the PWM pulses, the PWM modulator should respond to the error amplifier voltage change as soon as possible. For a given system, the phase inductor current slew rate is fixed, set by the input voltage, output voltage and inductance.

To obtain a faster total inductor current slew rate, more than one phase can be turned on simultaneously. This requires the PWM modulator to allow phase overlap and turn on additional phases proportionally to the step load. Based on these observations, the PWM modulator plays an important role in achieving fast transient response.

Fig. 2 shows a typical voltage regulator with a conventional trailing-edge PWM scheme. In trailing-edge modulation, the error amplifier output (VCOMP) is compared to a ramp signal to generate the PWM signal. To reduce the noise impact and avoid multiple PWM pulses in one switching cycle, an R-S flip-flop is typically used. However, the R-S flip-flop brings an additional response delay to the system.

The worst-case delay would be in the trailing-edge modulation scheme, when a PWM pulse is turned on by the clock and terminated by the intersection of the ramp signal and VCOMP. Therefore, the modulator cannot respond to a change after PWM goes low until next cycle.

As shown in Fig. 2, VCOMP may jump above the ramp signal at T3; however, the PWM signal stays low until the next clock pulse at T4, resulting in a turn-on delay (TDELAY). The turn-on delay can cause extra voltage drop in the event of load step. The trailing-edge modulation scheme can respond quickly to any change when the PWM pulse is high, so it can turn off the PWM pulse without delay. Therefore, the trailing-edge modulation scheme has an excellent turn-off response but a poor turn-on one.

Advanced Pulse Positioning

Conversely, the leading-edge modulation scheme has an excellent turn-on response but a poor turn-off response. Conventional dual-edge modulation, based on a triangular-ramp waveform, provides significant improvements over either of the single-edge schemes, but can still have half-switching-cycle delays for the turn-on and turn-off edges. Based on this observation, the APP PWM scheme is introduced to minimize both turn-on and turn-off delays by combining the benefits of the trailing-edge and leading-edge modulators. The block diagram and operational waveforms of this scheme are shown in Fig. 3.

The APP scheme has a down-ramp signal (VRAMPDOWN), which is the same as the ramp in the conventional leading-edge modulator. When VCOMP becomes higher than VRAMPDOWN, a single pulse is generated at the one-shot's output (labeled SET) to trigger the R-S flip-flop and start a PWM pulse at T1, as shown in Fig. 3. Once the PWM signal goes high, another ramp signal, VRAMPUP, starts to increase with a fixed slew rate. When the voltage of VRAMPUP equals the voltage of the VCOMP signal, it will terminate the PWM pulse at T2. Therefore, the PWM duty cycle depends on VRAMPUP and VCOMP, just as it does in the conventional trailing-edge modulator, while the PWM pulse position is determined by VRAMPDOWN and VCOMP, which is similar to the conventional leading-edge modulator. The APP PWM modulator has the advantages of both the leading-edge and trailing-edge modulators. The PWM pulse can be turned on and off at any time with minimal delay.

Free from the limits of the clock-signal triggering, the APP modulation scheme can respond to the change of the VCOMP signal instantaneously. If the transient event happens, and the error amplifier output VCOMP increases and intersects VRAMPDOWN at T3, the PWM pulse will start to increase the inductor current instantaneously. At T4, the voltage on VRAMPUP equals the voltage on VCOMP, and the PWM pulse stops without any delay. Therefore, the system can respond to the transient event and settle very rapidly.

Reducing Output Capacitance

To increase the inductor current slew rate in multiphase applications, it is preferred that more than one phase be turned on simultaneously, based on the transient step load. The APP scheme is excellent for this demand. As shown in the left side of Fig. 4, all phases are turned on when VCOMP jumps very high in response to a large output-voltage change associated with a high di/dt load step. Since the total inductor current increases very fast and reaches the load current quickly, the current drawn from output capacitors is reduced. The voltage regulator with the conventional trailing-edge modulation scheme will need more output capacitors to provide additional current when the total inductor current increases slowly, as shown in the right side of Fig. 4. A similar case could be examined for leading-edge modulation on a load stepdown.

Intersil has introduced a family of multiphase controllers based on the APP modulator. One typical application circuit of a voltage regulator with the ISL6312A is shown in Fig. 5. The ISL6312A employs the APP modulation scheme to achieve excellent transient response with reduced bulk output capacitors. With three internal drivers, ILS6312A can build a compact solution with higher performance and lower cost than traditional multiphase modulators. Some other advanced features of ISL6312A include differential remote-voltage sense, differential phase-current sense, phase-peak-current limit and a load-current indicator function.

With the APP modulator, the transient response of the voltage regulator is improved significantly. Without extra delay and an extremely fast transient response, the switching frequency can be reduced to increase efficiency without sacrificing transient performance. Due to the simultaneous all-phase-on feature, larger-output inductors can be used to reduce the ripple phase current. Or, with the same output inductor, the output capacitors can be reduced to meet the same transient requirement. Furthermore, the benefits of using coupled inductors can be further improved with the APP modulator. Typically, ceramic capacitors are used to absorb the initial voltage spike caused by the fast load current slew rate and the ESL impact of the bulk capacitors. Therefore the selection of the ceramic capacitor is similar to that of the conventional voltage regulator. However, the fast current slew rate of the total inductor current during a transient event will reduce the demand on the bulk capacitor ESR. Therefore, a less-expensive bulk capacitor solution can be employed in the voltage regulator with the APP modulator.

With conventional modulation schemes, the ESR of the bulk capacitor must be less than the desired loadline value. For a typical 1-mΩ loadline design, the equivalent ESR of the bulk capacitors should be around 0.7 mΩ for the voltage regulator with a conventional modulation scheme. If 7-mΩ bulk capacitors are employed, this equates to a requirement of 10 bulk capacitors. With the APP modulator, the equivalent ESR of the bulk capacitor may be chosen above the desired loadline, depending on the output inductor value. In the following 4-phase design with a 1-mΩ loadline, the equivalent ESR of the bulk capacitors is only 1.17 mΩ, equivalent to six 7-mΩ bulk capacitors in parallel.

Transient response test data on a 4-phase voltage regulator is included in Fig. 6. With only six bulk-output capacitors (680 µF), the voltage regulator based on the ISL6312A using APP met the stringent transient response requirement, while 10 bulk capacitors (560 µF) were needed in the voltage regulator with the conventional trailing-edge modulator. The capacitance values of individual bulk capacitors are different for the two regulators. However, the ESR value, which determines the undershooting characteristics, is the same for both capacitor types.

As can be seen in the left side of Fig. 6, all phases are on immediately to provide the maximum total current slew rate from the output inductors when a 100-A load step is applied to the system. All phases are then immediately off at load release to reduce the inductor current as soon as possible, as shown on the right in Fig. 6.


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