Current sharing or load sharing between two or more power converters now employs analog techniques. AC-DC and isolated dc-dc power supplies operating in redundant configurations, or power supplies connected in parallel to boost supply current, are usually required to share the load equally. This spreads the electrical and thermal system loading, reduces the likelihood of system hotspots and improves overall reliability. Such a current share scheme must be fault-tolerant, provide good transient response and be standardized to allow the end-user to mix sources from various suppliers.
The most commonly used current share scheme often is referred to as a “highest-drives-the-bus” system. Fig. 1 shows an implementation of this scheme using a controller and monitor IC, such as the ADM1041. The parallel power supplies use a current share output pin to connect to each other. This analog output is a measure of the current load supplied by each power converter. Initially, the power supply with either the highest output voltage set point or the lowest impedance path to the load will attempt to supply most of the load current. This unit becomes the “highest” or leader; the voltage on the current share bus represents the current supplied by the leader. The other parallel units compare their supplied current with the bus voltage and then change the voltage reference and output set point to supply more current. Gradually, the system reaches an equilibrium point, and the units share almost equally. An offset usually is introduced into the system to provide some hysteresis and avoid units constantly swapping the “highest” position. Essentially, one unit will take slightly more current than the others at the steady-state point, preventing oscillation between units or what's known as “hunting.”
Other forms of current share use master-slave approaches, droop or passive current share, and even thermal sharing. The “highest-drives-the-bus” method most commonly is used because of its simplicity, accuracy, reliability and fault tolerance.
DIGITAL CURRENT SHARE
Recently, there has been a proliferation of digital control ICs that are DSP or finite state machine-based. These generally employ CMOS or BiCMOS low-voltage processes that require a lower supply voltage than previous analog power ICs in the 3-V to 5-V range. Customer specifications for an analog share bus vary, but a common requirement is 8 V at full load supply. This is above the maximum voltage of the digital IC. Designers looking to enjoy the flexibility and features associated with newer digital ICs are penalized with the addition of components, placement costs and associated reliability impact. Fig. 1 is an example of the increased component count surrounding the ADM1041 low-voltage CMOS controller.
In any current share implementation, the system load often can be distant from the power source. In an analog share scheme, the return path is susceptible to noise injection that can lead to reduced accuracy of the current share scheme. The digital solution provides greater immunity to noise introduced on the current sense return. In turn, this leads to improved share accuracy across the load range.
The proposed current share scheme communicates a digital word representative of the current supplied for a power supply unit. The scheme works in exactly the same way as the analog “highest drives the bus,” except that a digital word is transmitted and compared to the current share bus.
Each bit inside the digital share word is defined to improve noise immunity and reduce the likelihood of erroneous data transmission (Fig. 2a): A logic ‘1’ defines a high-low transition at the start of the bit and a low-high transition at 75% of tBIT. A logic ‘0’ defines a high-low transition at the start of the bit and a low-high transition at 25% of tBIT.
The data frame, shown in Fig. 2b consists of one start bit, eight data bits indicating the current information and two stop bits. The start bit is always a logical ‘0’ and the two stop bits are always ‘Idle’ bits. Because there is no addressing, this frame repeats all the time at a frequency of approximately 10 kHz.
The bandwidth of the share loop is expected to be an order of magnitude lower than the power-supply voltage control loop, as in existing analog current share schemes.
100-W EVALUATION KIT
The digital current share scheme is demonstrated here using a 100-W evaluation board shown in Fig. 3. The board converts a 48-V input to a 12-V, 8-A output. This is a relatively low power implementation, but the concepts can easily scale to higher power levels. The dc-dc isolated topology used on the 100-W board is full-bridge with zero voltage switching and secondary synchronous rectification. The digital controller, Analog Devices' ADP1043, controls the feedback loop and drives the primary bridge and secondary synchronous rectifier FETs. The ADP1043 also controls the drive to an OR-FET, connected in series with the output rail, for redundant fault protection during parallel operation. The digital controller provides the option of traditional analog current sharing or digital current sharing between parallel power supplies.
Figs. 4a and 4b show real-time measurements of the digital share bus. The first plot shows a power supply unit operating in isolation and supplying the full load current. Note that the bus is actually an inversion of the unit's output due to the open drain bus connection. Fig. 4b shows the change in output current of the parallel units until they reach an equilibrium point. Fig. 4c shows the effect on the bus when a second power supply is hot-plugged, connected in parallel. The current share word on the bus now changes to half of the original value, indicating that the two parallel units now equally share the system load current.
The latter figure illustrates some important practicalities related to the digital frame transmitted to the bus. The ‘Idle’ period is marked by two blank pulses at the start of the current share frame. During start-up of the power supply, the first unit to detect either two stop bits or the idle period can transmit and control the bus, if only for a short period of time. The first device to detect ‘Idle’ pulls down the bus and begins the current share frame. All power supply share bus signals synchronize at this time. After start-up, the bus signals synchronize to the fastest signal transmission, usually dictated by the master clock.
Similarly, if a power supply unit is hot-plugged onto the bus, the device cannot write to the bus until it detects the “idle” period. If the controlling device or lead device is unplugged during a mid-data write, then the bus immediately becomes idle. The first devices to sense the ‘Idle’ period (around 20 µs) write to the bus and the share process is re-established with minimum interruption.
Remember that the protocol speed of 10 kHz is much faster than the speed of the current share control loop. Hence, minor disturbances have little or no effect on the current share operation. If, for example, two units are sharing, and unit 1 initiates a “start” but unit 2 is immediately unplugged, then the data transmitted will not match the actual current share status for one frame transmission.
When two or more units share, the lead position can be handed back and forth between power supplies. This is sometimes called “hunting” between the supplies and is observed as a low-frequency oscillation dependent on the bandwidth of the current share loop. In analog current share schemes, an offset is introduced to ensure that the “highest” unit remains in control of the bus after steady state has been reached. Similarly, in the digital share scheme, offset is introduced based on the least significant bit (LSB) of the current share word. If the system is relatively low power or noise-free, then the designer may be able to operate to one LSB of offset or difference. The units share to within an accuracy of one LSB and will not attempt to improve further. In a noisy environment, the designer has the option to increase the offset to more LSBs. This decreases the share accuracy between units but eliminates hunting. Because the digital current share accuracy is less likely to be sensitive to ground return noise, this feature can be adjusted to improve load sharing accuracy at full loads and to improve light load sharing operation compared to existing analog current share schemes.
As mentioned, the digital current share scheme works in the same way as the traditional analog scheme — “highest drives the bus” — except that the current information is a digital frame rather than an analog voltage level. Similar to the analog equivalent, the digital scheme remains tolerant in the event of a failed unit, which is isolated from the bus and cannot pull the bus down. In the event of a share bus failure, the parallel units will continue to operate and will likely move to inherent passive sharing. In this event, the accuracy of the share capability depends on the relative set point of the output voltage and the inherent load line (or series impedance). Other forms of secondary protection, such as share good detect or supply overcurrent, should be considered to protect the system from damage.