Pulse-width-modulation (PWM) duty cycles above 50% require a compensating ramp — called slope-compensation — to avoid instability. With traditional slope-compensation solutions, it is difficult for the switching converter maintain stability for duty cycles approaching 100%. A new technique using negative resistance provides better results at duty cycles near 100%.
REVIEWING SLOPE COMPENSATION BASICS
To understand how this new technique works, we have to review the basics of slope compensation. Fig. 1 shows a diagram of a typical slope-compensated PWM converter. The clock produces the basic switching frequency. Its narrow pulse sets the flip-flop (F-F) which, in turn, activates the driver and turns on the main MOSFET switch. This begins the switching cycle.
While the switch remains on, current ramps up and so does the voltage across the current-sense resistor. When the voltage across the current-sense resistor equals the internally-generated current-threshold voltage, the comparator resets the F-F. The main switch is turned off and remains off until the next clock pulse begins a new cycle. During steady-state operation, the error amplifier outputs a fixed voltage that is compared with the voltage across the current-sense resistor. Without slope compensation, this voltage would be fixed. With slope compensation, this voltage reference is ramped downward by the slope-compensation current source. In this simple diagram, the downward slope is linear.
Clearly, as D increases so does the magnitude of the slope compensation, and the shape of the needed slope compensation looks like Fig. 2. D = 0.5 requires no slope compensation, but as D increases it needs more. As D approaches 100%, the PWM circuit requires the maximum amount of slope compensation.
A popular method for slope compensation is to add a portion of the PWM timing-capacitor ramp voltage to the current-sense voltage. By properly scaling the magnitude of this capacitor ramp, stability can be assured for all duty cycles above 50% (Fig. 3.)
For most applications where the duty cycle of the switching converter ranges from about 40% to 75%, the use of the exponential voltage on the PWM timing capacitor is a perfectly acceptable way to get the needed slope compensation. The timing-capacitor voltage starts at zero at the beginning of the period and ramps toward 5 V. When its voltage reaches 2.5 V the period ends, the PWM signal shorts out the capacitor, and the timing for the next cycle begins.
WHAT'S THE PROBLEM?
But for those special applications that require D to reach 95% or higher, there may be a problem. Consider two possible waveforms on the PWM timing capacitor: one is the conventional exponent with a negative exponent, and the other a combination of both a negative exponent and a positive exponent. Either of the two timing-capacitor waveforms in Fig. 4 can be appropriately scaled to give the desired slope compensation, so why consider the more complicated shape on Fig. 4b? The simple answer is that the shape and slope of the negative exponent in Fig. 4a is completely opposite to the ideal shape shown in Fig. 2. In other words, for duty cycles less than the maximum, the shape of slope compensation in Fig. 4a gives much greater slope than needed; often three to five times more. The penalty is that all this excessive compensation eats up a huge portion of the current-sense voltage range.
On many PWM controllers, the voltage on the current-sense input (CS) is limited to some maximum amount, say, 1 V. The usual goal is to have the voltage-swing across the current-sense resistor use up as much of this 1 V as possible. However, in some cases the slope compensation takes up a substantial part of the 1-V window, thus decreasing the sensitivity to actual switching current. The problem may arise if the switching converter is operating at duty cycles close to 100% and the capacitor waveform at Fig. 4a is used for slope compensation. As D approaches 100% the waveform in Fig. 4a has a slope of only 1.74 V/s, and if compensation began at D ≤ 0.5, then the change of voltage on the capacitor is about 1 V. Once this waveform is properly scaled, there may be only slightly more than 60% of the current-sense voltage available for actual current sensing.
The poor result above is for slope compensation which is 1.4 times the minimum and begins at D = 0.5, but some designers use twice the minimum, which causes the CS window to shrink by nearly 50%. And, worse yet, some slope-compensation designs use the entire timing-capacitor ramp beginning at D = 0, with the result that virtually the entire CS window is used for slope compensation.
COMPOSITE TIMING WAVEFORM
With this new technique, the downward slope of the ramp increases with time during the switching cycle. The minimum amount of slope compensation is simply half the difference between the down-slope and the up-slope. Thus for duty cycle D = 0.67 the current down-slope is twice the up-slope, so the minimum slope compensation is 50% of the up-slope (or 25% of the down-slope). This is the minimum compensation, which implies that any current disturbance will not grow with time. It also means that a disturbance will not die down with time. For this reason, circuit designers provide 25% to 100% more than the minimum compensation to assure that any disturbances are quickly squelched.
Now consider the composite waveform in Fig. 4b and the simple circuit in Fig. 5. Capacitor C begins the timing cycle with its voltage at zero. Switch S1 is open so the capacitor begins normal charging through resistor Ra toward a final voltage (V1). When the capacitor voltage reaches V2, S1 closes to switch in negative resistance (-Rb). If the magnitude of -Rb is less than Ra, the net result is a negative resistance, which continues to charge C. For example, if Ra is 10 kΩ and -Rb is -5 kΩ, the result is -10 kΩ and C continues charging toward infinite voltage with ever-increasing slope.
The components above are selected so that for 0 ≤ D ≤ 0.5, the waveshape is that of an ordinary RC circuit, but for 0.5 ≤ D ≤ 1 the waveshape is that of a capacitor being fed by a negative resistor. Clearly, the shape of Fig. 4b from D = 0.5 to D = 1 more nearly resembles the actual required slope compensation curve of Fig. 2. At D = 0.5 the amplitudes and slopes of the composite wave-shapes match, and the positive exponent is chosen to give V = 2.5 volts at D = 1 for the practical example circuit in Fig. 6. The important result is that at D = 1, the slope of waveform Fig. 4b is a much greater 4 V/s. This means that, despite a slightly larger ΔV from D = 0.5 to D = 1, after appropriate scaling, much less of the voltage swing on the current sense is occupied by this new waveform. In fact, 75% or more of the 1-V swing is available for current sensing if the compensating waveform is 1.4 times the minimum.
EXAMPLE CIRCUIT
For the example circuit in Fig. 6, the PWM begins a cycle with C1 discharged to 0 V, and the cycle ends when the voltage on C1 reaches 2.5 V. The switching frequency is chosen to be 125 kHz. At the beginning of the cycle, C1 starts an ordinary RC charge waveform toward 2.5 V because of the resistor divider combination of R1 and R2. If R3 = R4, when the voltage on C1 reaches about 1.2 V (the sum of the base-emitter voltages of Q1 and Q2), Q1 and Q2 begin to conduct and the collector current of Q2 makes the equivalent charging resistance of C1 look negative.
From D=0 to D=0.5, the values of R1, R2 and C1 are chosen such that when D=0.5 (4 µs in this example), the voltage on C1 is equal to the 1.2-V turn-on threshold of the negative resistance circuit. After Q1 and Q2 begin providing positive feedback, the equivalent negative resistance is selected to cause the voltage on C1 to arrive at the 2.5-V RC threshold of the PWM at D=1 (8 µs for this example). In this circuit the positive resistance is the parallel combination of R1 and R2, or 19.2 kΩ. For D ≥ 0.5, the required negative resistance is about -13.8 kΩ, which implies a negative resistance of -8 kΩ in parallel with the positive 19.2 kΩ. If there were no losses and infinite transistor Beta, the value of R5 would be about 8 kΩ. However, accounting for practical circuit parameters, R5 must be about 15% to 18% lower or about 6.81 kΩ.
Transistor Q3 is used to provide slope-compensation current and it does not begin to activate until D = 0.5, just like Q1 and Q2. R7 and C2 are usually chosen to give about 50-ns of filtering to screen out turn-on spikes across the current-sense resistor. To give appropriate slope compensation, the value of R6 (in combination with R7) is chosen to give the desired compensation.
This basic configuration is somewhat sensitive to temperature variations and component tolerances. Of course, it could be much more accurate if it were made from matched transistor pairs and current mirrors. This might be an option for PWM manufacturers.
Clearly, many obvious variations are possible by changing resistor values or adding resistors. With all the possible combinations and variations, this could be considered a universal circuit for slope compensation. For example, if Q2 and R5 were not populated, then ordinary slope compensation could be made using the standard RC timing without negative resistance.
Of course, the ideal slope compensation scheme would be to apply slope compensation only in the vicinity of the threshold. If this were done, then slope compensation would occupy only a small part of the available voltage range of the CS circuit of the PWM. This vicinity compensation scheme would require rapid adaptive control so as to be able to quickly cover the entire range of expected duty cycles. Such a scheme is beyond the scope of this article.
REFERENCES
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1979 U.S. patent 4,148,097, “DC to DC Converter Utilizing Current Control For Voltage Regulation”
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1978 PESC conference Record, “Simple Switching Control Method Changes Power Converter into a Current Source”
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TI Unitrode Application Note SLUA101