Optimizing Ripple for a COT Buck Converter

One of the key challenges when designing a constant-on-time (COT) buck converter is to make it stable with low-ESR output capacitors. Although the basic theory of voltage-mode hysteric converters expects the output voltage will be greater after turning on the high-side switch, it shows a limited cycle oscillation on the output if the ESR of the output capacitor (ESRo) is not enough to meet this expectation (Fig. 1). Such a limited cycle oscillation should be prohibited, even if it is not catastrophic, to maintain output quality.

EMULATED RIPPLE INJECTION CIRCUIT

Article Equations

Although there are devices manufactured by some semiconductor manufacturers that generate emulated ripple within the IC^[1], most COT converters, on behalf of ESRo, require external emulated ripple injection (ERI) to be compatible with low ESR output capacitors^[2]. This article aims to help designers select components not only for preventing limited cycle oscillation but for optimizing ERI circuitry performance.

In the frequency domain, ERI makes a similar response in the high-frequency range around the switching frequency, similar to how the ESRo makes a zero in that range. It also shows different responses with ESRo in the low-frequency range. Consequently, its total frequency response differs somewhat compared to just the ESR zero (Fig. 2).

In the time domain, a fast response when the load changes from light to heavy can be achieved when the COT converter exhibits its maximum bandwidth, defined by fixed on-time and minimum off-time during T_R (Fig. 3). So, it is required to analyze the sensed voltage on feedback (V _FB) during load transient in the time domain.

Fig. 4 shows the output-stage circuit — including ERI — assuming a low-ESR capacitor and a low-DCR inductor. For the worst-case analysis, no-load and zero-ESR is considered. Therefore, the phase-shift at the corner frequency of the output filter is 180 °. To find the V _SW to V_O transfer function, V_SW can be divided into a voltage-controlled current-source I_L and a voltage-controlled voltage-source V_O (Fig. 5),

where:

and

Based on superposition theory, the I_L to V_FB transfer function can be calculated after shorting voltage source V_O, and the V_O to V_FB transfer function can be calculated after opening the current source I_L.

Consequently, the sum of the outputs is:

and its double-pole frequency is:

The definitions of G_HF(s), G_LF(s), R_F, and A_F are:

AMOUNT OF EMULATED RIPPLE

Where, G_HF(s) has two poles. Its higher-frequency pole is:

and the lower-frequency pole is:

In the high-frequency range, G_HF(s) is dominant because its order of numerator is larger than the order of denominator. The eESR, the amount of emulated ripple on V_FB in the scale of ESR, can be represented as:

MAKE NO PHASE-LEAD OF eESR(s) AT F_SW

G_HF(s) has a phase shift which starts from -90° to -270°, whereas G_LF(s) has one zero and one pole. Unless placing F_P1 below or:

PREVENT LIMITED CYCLE OSCILLATION

G_HF(s) creates additional phase shift which results in surplus oscillation on the output because the phase is dominated by the bigger gain transfer function between G_HF(s) and G_LF(s). Approximately, the criterion for dominating G_LF(s) at F_DP is:

eESR(s) has one double zero at its origin and two separated poles. eESR(s) can act as a pure resistive impedance if it has no phase-lead at F_SW. It is possible to place F_P1 below F_SW/10. Such a phase-lead at F_SW makes the small falling slope of emulated ripple, which results in larger jitter. Assuming F_P1 is below F_SW/10, eESR(s) at F_SW can be simplified as:

Based on COT theory, to prevent limited cycle oscillation:

DISPLAY MAXIMUM BANDWIDTH WHEN LOAD CHANGES

Considering the feedback-resistor-divider's attenuation, the criteria to prevent limited cycle oscillation becomes:

From Eq. 15, we may select an excessively small R_RC_R, as it does not have a negative effect on output ripple, but such a large emulated ripple results in poor line regulation and load transient. Some devices normally require 15 to 30 mV of minimum ripple (V_minRIPPLE) on the feedback node to minimize jitter on the switch node and ensure noise immunity. The criterion to minimize jitter and ensure noise immunity is:

In the time domain, our focus will be to minimize the overshoot/undershoot when there are sudden changes in load current. Assuming the load changes from light to heavy, such a fast transient response can be achieved as V_ERI — consequently V_FB — dominantly follows V_O rather than V_CR, so the sum of V_O and V_CR (V_ERI = V_CR + V_O) is less than the reference voltage during T_R (Fig. 3). To ensure V _ERI dominantly follows V_O during T_R:

Alternatively,

The criteria to ensure V_ERI dominantly follows V_O when the load changes from heavy to light is:

Alternatively,

Where

is the averaged slope of I_L during T_R during light to heavy load changes.

is the slope of I_L during heavy to light load changes.

EXPERIMENTAL RESULTS

is the minimum off-time of the IC.

REFERENCES

I_minSTEP, the load step during load transient, should be selected as a minimum load step in a considerable load-step range because after optimizing, the converter will show its max bandwidth if the load step is bigger than I_minSTEP, but cannot show its max bandwidth if the load step is smaller than I_minSTEP. Setting I_minSTEP as half the max load current is a good starting point.

Figs. 6a to 6c show output voltage with a load transient. While enough ripple to prevent limited cycle oscillation is injected in all cases, Fig. 6c limits oscillation, undershoot/overshoot due to limited bandwidth, and unwanted oscillation due to phase shift that can be cleared by optimizing external components.

Summary of Design Criteria for External Ripple Injection