Find a downloadable version of this story in pdf format at the end of the story.
Microstepping a two-phase stepper motor requires the winding currents to be 90° out-of- phase so that the stepper functions like a synchronous motor with ac applied. That is, the phase A current is cosine (90° ˊn/64) and the phase B current is sine (90° ˊ n/64), where n is the number of steps. “Synchronous” motor operation is obtained by approximating a sinewave via pulse-width modulation of the coil currents, as shown in Fig. 1 for a 1/16-step “sinusoidal” drive.
Performance benefits for microstepping include quiet and smooth rotation even at low speeds. Unlike the more expensive boards and boxes usually associated with microstepping, monolithic power ICs are physically small, inexpensive, practical, and programmable. Hardware and software costs have decreased and, in turn, this has stimulated the expanded application of fractional stepping. Automated business systems, computer peripherals, and similar equipment have been the primary impetus propelling the design and the manufacture of monolithic power ICs and multichip modules to drive small-to-medium size step motors.
A new, dual bridge power IC, the A3972, is capable of ±1.5 A per bridge with a 50V maximum rating can provide the necessary microstepping drive. This IC operates from a serial data bus, integrates eight low on-resistance NMOS outputs, and the programmable control of various chip functions. These include two 6-bit, linear DACs for current control, synchronous rectification modes to reduce internal heating, recirculation control, undervoltage and thermal protection, inputs compatible with 3.3V and 5V, and other circuit functions. Before detailing the operation of this device, the necessary microstepping characteristics will be described.
An important consideration for microstepping systems is what is called “empty resolution,” or “empty stepping.” Though step division ratios (SDRs) ranging from 8 to 256 are offered in the high-cost board or box-level hardware, open-loop designs cannot benefit from theoretical SDRs and subdivisions beyond 1/10th. Motor accuracy, with various errors, could equal ±3%. Without any positional feedback it becomes formidable to envision subdividing beyond 1/16th to 1/32nd. Further, detent torque and/or mechanical factors obviate high-resolution positioning, and offer a clue to the futility of dividing a full-step into 256.
Even ignoring the load, 7-8 microsteps (more if detent torque exceeds 5%) are needed to equal 5%. Hence, no motion occurs until the motor torque eclipses detent torque and stepper loading, and this usually entails at least 10-20 microsteps or more (when the step division is 256).
Clearly, the current ratios in Table 1 demand very high-resolution digital-to-analog conversion of ≥15usable bits to control the phase A current for the initial microsteps. The ≥15-bits are necessary to resolve voltage differentials that are 300µV between microsteps #1 and #2 (assuming a 5V DAC reference). The smallest voltage increment of 100µV relates to the current in phase A from 0 to microstep #1. For 15 bits and a 5V reference the smallest change is ≈153µV (5 ÷ 32,768); thus, even15-bits cannot provide the “precise” voltage for either extreme of this 256 step subdivision of one full-step.
Obviously, 256 microsteps only entails 8-bits if the current ratios follow a linear relationship, however, achieving the 256 microstep resolution necessitates ≥15-bits to approximate the smallest incremental currents. Only 256 of the 32,768 are useful, but this permits tailoring the current profiles to suit the step motor (characterizing the step motor is imperative for open-loop designs).
PWM OUTPUT CURRENT CONTROL
Designing with 16-bit DACs is not complex, nor costly, however, delivering the phase current ratios needed for equidistant increments from one microstep to the adjacent step is a rigorous challenge. Creating the proper current ratios necessitates an expensive, extensive evaluation of the motor, but pales when contrasted to the difficulty pertaining to precisely regulating the PWM winding currents over 256 microsteps. Using the cosine/sine table as a reference point, and a microstepping power module (±1.6 A peak, ±1.0 A rms), the phase current increments can be calculated. The ±1.0 A rms limit equates to ±1.4 A and 100%, the one-phase, constant current drive of Table 2 that shows microsteps #1 to #16 of a 256-microstep sequence. Applying 1.4A as the 100% value for phase A, the need for high-resolution current control is absolutely unmistakable, especially when listing the current changes from microsteps #1 to #16.
Detent torque, load, inertia, plus friction are factors that support the futility of high-resolution microstepping. Empty resolution is an absolute reality for those open-loop microstepping systems that endeavor to subdivide a full-step into minute fractional increments (>16 microsteps).
Perhaps the utmost challenge of microstepping is the designer's ability to precisely control phase currents within the minute variations essential for high-resolution microstepping (≥32 microsteps). The vagaries and variances in the performance of power electronics, especially bipolar transistors, cannot be ignored. The ability to subdivide 6.25 mA (microsteps #1 to #16) changes in phase A is expensive and impractical to develop and produce. Given the tolerances in motor qualities (inductance, resistance, etc.), the dynamic response of the circuitry, stability of the DAC reference voltage, etc.; the real probability of attaining the current control (<0.01%) needed for minute changes in current converges on zero.
Another indicator is that microstepping drives do not include any minimum/maximum specifications (± current limits) for high-resolution PWM operation. Even with linear current control, which is very inefficient, the basic ability to achieve <0.01% increments in the phase currents is very doubtful; and any precision PWM current control is very exacting and formidable.
MICROSTEPPING POWER IC
As power ICs evolved, the level of integration has vied with two significant, vital concerns: (1) higher pin counts are required, (2) the package thermal ratings must be reduced and/or internal power dissipation decreased. The A3972 microstepping power IC contends with these issues and is a low-cost, monolithic solution for many new step motor systems. It is a dual, full-bridge, PWM microstepping motor driver (Fig. 2). Its 3.1W package power rating correlates to a thermal resistance of 40°C/W.
This step motor drive IC integrates control circuitry and eight high-current NMOS outputs on the chip. The IC is fabricated from a merged bipolar and CMOS silicon technology. The outputs form the two full-bridges required for powering a step motor in a bipolar configuration. This power IC provides PWM control of the phase currents, and the designer programs the output current, and other functions, via a serial input bus. This alleviates the power IC pin count, otherwise its 24-lead package would be woefully inadequate for a dual full-bridge motor driver.
Continue to next page
The basic functions and features of this new power IC are:
- Serial data bus control driver funtions
- Low on-resistance NMOS FET outputs
- Microstepping control via two 6-bit linear DAC
- 4 MHz internal oscillator for device timing
- Programmable recirculation (current decay)
- Synchronous rectification reduces IC heating
- Crossover (shoot-through) current protection
- Thermal and undervoltage protection
- Compatible with 3.3V and 5V input logic
- Internal, precision 2V reference
- Sleep/idle mode for power/heat reduction
The A3972 is controlled by a three-wire serial data bus, but minimizing the needed signal inputs adds to the controller's complexity. Serial data entry for the programmable functions permits considerable flexibility in controlling the motor PWM current regulation, but also requires a microcontroller or other control/logic to supply the necessary serial data.
Attempting a parallel-input version integrating the same functions and features would necessitate a 32 lead-count package. Although the three-wire serial-input design demands two 19-bit words, a dedicated microcontroller, usually an 8-bit low-cost version, is an effective/efficient method for exploiting microstepping. The overall expense of the driver IC, plus the 8-bit microcontroller, is considerably lower than any systems design based on using boards,boxes, or power modules.
Serial data is clocked into the shift register on the rising edge of the CLOCK signal. Normally, the STROBE input would be held high, then only switched low to initiate a write cycle. The data is entered with the MSB first, and trailed by the word select bit. Although entering 19 bits entails three 8-bit words with a low-cost microcontroller, the relatively slow update rate for a step motor normally is of little consequence.
As the upper (sourcing) output switches on, a current spike may occur due to the reverse recovery of the output FET body diodes and/or transients that correlate to the load's distributed capacitance. To prevent current spikes from false triggering the comparator, and resetting the sourcing output latch, the input to the comparator is blanked after the off-time counter has elapsed. Subsequently, the latch is reset after the PHASE (direction) input changes state (the current direction is reversed).
Synchronous rectification may be the foremost attribute of this motor drive IC. Synchronous rectification can only work when the off-time cycle is triggered, either by a control signal that disables the bridge conduction, or the internal fixed off-time cycle. Motor current recirculates based on the programmable decay mode. Synchronous rectification entails switching the MOS outputs on (conducting in the reverse direction). Shunting the internal body diodes diminish the IC's power and heating. Low on-resistance FETs develop a lower voltage drop than the body diode forward voltage, which can substantially lower the IC power dissipation and junction temperature.
The IC can be switched into a low-power (idle) mode by entering a “0” to D18. This disables all outputs, the charge-pump turns off, and the supply currents (load and logic) reduces to very low values. The undervoltage monitoring circuitry remains active while in this mode.
An on-chip supply voltage delivers the proper gate drive to the low-side FETs. Internally, the supply is monitored, and with any fault condition, its outputs are disabled. This pin should be decoupled with a 0.22 pF capacitor to circuit ground.
An external 3V (max) dc reference voltage can be applied to the REF terminal or the IC's precision, internal 2V reference can be used. The combination of reference and current sensing resistor limits the maximum (100%) phase current.
The 6-bit DAC input code extends from 1 to 63. The Range value is either 4 or 8, and is controlled by D18 of Word 0. Programming the DAC to “0” disables the NMOS outputs and also induces fast-decay recirculation. With the 6-bit DAC, any incremental change in current is 1.43% (90° ÷ 63); 3.1% as the lowest.
Based upon the torque curve in Fig. 3, the input ratios for most rotor positions could compensate for the undershoot and overshoot if they are factored into the current profile. With a 1/16th stepping mode, this can equalize the incremental rotor displacement during microstepping. However, a very thorough evaluation of the step motor torque/displacement properties is a prudent prerequisite for success.
The PWM timer is programmable through the serial port, and furnishes fixed off-time signals to the control circuitry. With mixed mode, the initial portion of the off-time is fast-decay until the time count limit is attained. Then, the remainder of the PWM cycle is slow-decay. When the fast-decay is set longer than the off-time, the recirculation remains in the fast-decay mode for the entire off-time interval. For the software developer, applying an automatic slow- and fast-decay simplifies programming without a loss in performance. Slow-decay for increasing current, and fast-decay for the decreasing half wave of the 360° microstepping cycle.
The PWM timer employs an internal oscillator (typically 4 MHz); but, also, will operate from an external oscillator that is connected to the OSC input. Three internal divider choices are programmable to afford users a degree of flexibility with the clock frequencies in the system. A precision resistor may be used to further tighten the frequency tolerance. System designs without any external resistor should ground this device input pin.
The terminal labeled SLEEP allows decreasing logic and load supply currents to very low levels: ≤100 µA and ≤20 µA, respectively. A zero at D18 (Word 1) disables all circuitry.
Any fault condition causing excessive junction temperature, or low voltage on the charge-pump or regulator input, causes the outputs to be disabled until the fault condition is remedied. At power-up, or due to a low logic supply, the IC is protected by undervoltage lockout (UVLO).
Synchronous rectification switches the MOSFET outputs back on after a suitable delay (600 nsec). This reconciles the dynamic properties of the MOSFET's body diode. Switching the MOSFET outputs back on during the recirculation period effectively shunts the higher forward voltage of the NMOS FET body diode(s).
Four distinct modes of operation can be activated via the serial input data entry of bits D14 and D15:
- Active Mode prevents reversal of load current by switching off the synchronous rectification when any zero current state is detected.
- Passive Mode allows a reversal of load current, but disables the synchronous rectification if the inverted motor current reaches the current limit set by the user.
- Disabled Mode in which the MOSFETs are not reactivated (on) during the recirculation period (off-time). This mode should only be employed if external diodes (four per bridge, eight per power IC) are incorporated as clamping protection. The needed recirculation paths then substantially lower the IC dissipation and internal heating.
- Low — Side Only Mode in which the MOSFETs are on during the off-time. This mode shunts the recirculating current around the MOSFET body diodes. Because the high-side FETs are not switching, only four external diodes are needed. The external diodes are connected in parallel with the high-side FET outputs. Schottky diodes are preferred because they offer the best performance/lowest chip heating for this mode.
Continue to next page
The Low-Side Only Mode is suggested for high-power drive applicationsbecause it saves the cost of two additional diodes per bridge. In this mode, the low-side NMOS are pulse-modulated during the current control operation. In all other operating modes the high-side FETs are switched in response to PWM off-time control signals.
Given the ±1.5 A current rating, synchronous rectification is an important factor, particularly for high-current applications. There are three essential elements of the chip power and heating that constitute total dissipation: MOSFET on-resistance and the motor current, motor voltage and the circuit load on this supply, and logic supply voltage and current rating. Of these three conduction losses, the output power dominates any power calculation. Dynamic or switching losses are very difficult to calculate or measure and not generally of serious consequence at normal stepping frequencies. Only the conduction losses are considered for this discussion, which also includes the recirculation period of the PWM cycle.
Clearly, the package power dissipation cannot support the ±1.5 A rating for each bridge. Also, the single-phase PWM current limit is ≤1.36A rms (972 mA × 1.414). Calculating a value based upon the increased on-resistance reduces the allowable current substantially.
Increased on-resistance from internal heating diminishes the allowable output current in each NMOS bridge. This must be factored into any calculation of the motor current limit, and is based upon an evaluation of the NMOS FET on-resistance and body diode forward voltage. The on-resistance data reveals an increase of 1.72 times the room temperature value at +150°C.
On-resistance vs temperature is illustrated in Fig. 5, and the decreasing forward voltage of the body diode is plotted in Fig. 5. Despite the compensating effect of a diminishing forward voltage, the allowable current is restricted by the chip temperature and increased on-resistance.
Therefore, with synchronous rectification, the rms current must be reduced to compensate for the internal dissipation/heating. Basically, during synchronous rectification, the internal power and heating from the conduction period equates with the recirculation interval (the reversed current is flowing through the reactivated MOSFETs). Thus, the allowable current must be reduced to remain within the package limitations.
If the allowable current is below the ±1.5A rating, other methods must he applied to attain the full current rating of this power IC. Adding external Schottky diodes to shunt the MOSFETs during recirculation, while also controlling the synchronous rectification, substantially lowers the internal dissipation/heating. Schottky diodes must be utilized whose very low forward voltage shunts the recirculation current around the body diodes. External Schottky diodes permit disabling the synchronous rectification mode to realize reduced internal dissipation in a cost-effective manner.
With their maximum on-resistance of 0.35Ω at +25°C, the low-side outputs require diodes with a very low forward voltage or the shunting will not be sufficient. Utilizing a high-current (≥2 A) diode ensures that most of the current is shunted through the external recirculation diodes, but only at currents above 700-800 mA.
The Schottky diode characteristics represented in Fig. 6 indicate the difficulty in selecting a diode appropriate for shunting the on MOSFETs during synchronous rectification. Overlaying linear on-resistance values for both low- and high-side MOSFETs, and factoring in the increased on-resistance from heating poses a substantial design challenge, especially for the low-side Schottky shunting each body diode.
In Fig. 6, the Schottky diode is a 2.0 A device with a maximum forward voltage of 0.62V, and a temperature limited to +125°C. Further, the thermal resistance of the SFPB-76 would allow an average current of 1.2 A at +75°C. Because the diode duty factor is ≤50%, this is sufficient to shunt the FETs at higher currents without using the synchronous rectification (Fig. 7).
With their maximum on-resistance of 0.55Ω (+25°C), the high-side MOSFETs pose less of an issue. The same Schottky type, in shunt with the upper outputs, ensures recirculation currents flow through the external diodes with load currents from above 700 mA (per phase).
Basically, any motor current above 700 mA necessitates external diodes, otherwise excessive heating is the likely result. Additional options to lower chip temperature include: adding heat sinks, connecting the power tabs to the maximum copper area, and/or combinations of such techniques.
Because the interactive temperature effects of higher on-resistance, decreasing diode forward voltage (external and internal), and/or heat sinks become very complex; the allowable output limit is ambiguous. Adding external Schottky diodes has the most effect upon increasing the current limit, but the complications regarding the low-side bypassing preclude pinpointing an exact current value.
The best imaginable improvement is twice the 572 mA rms value, and this is based on the Schottky diodes completely shunting the recirculation currents. This equates to the MOSFETs conducting 50% of each PWM cycle, and the diodes shunting the other 50%.
Because the recirculation mode (slow-, fast-, or mixed-decay) is a significant constituent in determining the actual (average) relationship between conduction and recirculation power, the resultant internal power dissipation is not easily calculated and therefore very difficult for the systems designer to determine.
Given all the various control possibilities, the designer may benefit from some pragmatic views on the application of this new microstepping IC.
Clearly, the step motor itself is a fundamental design issue. Given specified accuracies of ±3% (PM hybrids) an open-loop step motor system is inherently limited to 32 fractional steps, but a much more realistic step division would be 16 and (per the various errors) ±3% is the absolute best possible accuracy throughout one full-step.
Empty resolution is real, and attempting to go beyond the practical limitations of the motor and drive circuitry only adds cost and complexity.
Though the application of mixed-mode decay can offer slight reductions in step motor heating, the additional evaluation involved is usually not worth the time and effort. The programming can be simplified by utilizing slow-decay during each ascending segment of the current waveform, and then switch to fast-decay for the descending portion of the current cycle. This technique avoids the necessity to evaluate any distortion in the phase current as the stepping frequency is increased (higher step rates demand an increased ratio of fast-decay in mixed-mode operation).
SYNCHRONOUS RECTIFICATION VS. OUTPUT CURRENT
Although some controversy may follow, using synchronous rectification at currents above those already mentioned is not recommended. Internal dissipation necessitates the application of Schottky diodes to reduce the device heating. Whereas the allowable output current involves various factors, the ambient temperature is often the most vital element in determining the critical current limit.
Continue to next page
Most designs specify +70°C as the ambient, so the prior calculations are valid. In designs requiring >600 mA (the rms value with microstepping operation), the recommendation is to disable the synchronous rectification and also add eight external Schottky diodes. Although cost increases, the lower device temperature results in a more dependable, reliable design solution.
Non-continuous applications (less than five seconds of motor operation, followed by disabling the stepper) allow higher currents, and relate to the duty factor. Applications of 600 mA allow synchronous rectification and do not need diodes.
Leenhouts, A., “Step Motor System Design Handbook, 2nd Edition,” Published by Litchfield
Engineering, Kingman, AZ, Copyright 1997.
Leenhouts, A., “Microstepping Today,” PCIM, April 1986, pp. 65-67.
McCarthy, K., “Getting More Out of Microstepping,” Motion Control, March 1991, pp. 12-16.
Emerald, P., “The Merits, the Mystique, and the Myths of Microstepping,” PowerSystems
World ‘98, AMD&C Proceedings, Santa Clara, CA, Nov. 1998.
Emerald, P., “The Merits, the Mystique, and the Myths of Microstepping (Part 2),” PCIM
Europe ‘99 Nurenberg, Germany, May 1999.
Emerald, P., Pickett, R., and Rowan, T., “Integrated ‘Mixed-Mode’ Microstepping Drivers
Afford Smoother, Quieter Operation and Reduce Motor Heating,” PCIM Europe ‘98, Nurenherg, Germany, May 1998.
Emerald, P., Peppiette, R., Seliverstiv, A., “Monolithic, Programmable, Full-Bridge Motor
Driver Integrates PWM Current Control and ‘Mixed-Mode’ Micrstepping,” PCIM ‘97, Hong
Kong, October 1997.
Allegro MicroSystems Paper STP-97-5A
Emerald, P., “Design Regimen for Resolving the Selection of Integrated Power Electronics for Step Motors,” Rocky Mountain Technology Expo, Denver, CO, April 1997.
Mazzola, T., and Floyd, R., “Intelligent Microsteppers for Stepper Motor Controls,” Motion Control, September 1991, pp. 16-21.
Reid, S., Lin, T., and Harju, D., “A Practical Insight of Fourth-Harmonics on Hybrid Step Motors,” Incremental Motion Control Systems and Devices Proceedings, June 1987, pp. 269-274.
Viegnat, N., “Microstep operation of Stepper Motors,” Motion Control, March 1991, pp. 48-50.
Thinksecap®, “Stepper Motor Drives,” Technical Publication from Portescap, Publication Date Unknown.
Download the story in pdf format here.