Digital Control Improves Bridgeless PFC Performance

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Due to the ever-increasing efficiency requirements, many power supply manufacturers are starting to look into bridgeless power factor correction (PFC) topologies. Generally, bridgeless PFCs can reduce conduction losses by reducing the number of semiconductor components in the line-current path. Although the bridgeless PFC is a concept that has been long on promise for many years, the difficulty of implementation and complexity of control prevent it from mainstream acceptance.

With the availability of low-cost, high-performance digital controllers that are specially designed for power supplies, more power supply companies are starting to adopt these new digital controllers for PFC designs. Compared with conventional analog controllers, digital controllers provide many advantages such as programmable configuration, non-linear control, lower part counts, and the most important, the ability of implementing complex functionalities, which are usually difficult for an analog approach.

Most present day digital power controllers, such as TI's Fusion Digital Power^™ controller UCD30xx, provide integrated power control peripherals and a power management core such as digital loop compensators, fast analog-to-digital converters (ADC), high-resolution digital pulse-width modulator (DPWM) with built-in dead-time, low-power consumption micro controllers, etc. They are good for a complex high-performance power supply design such as bridgeless PFCs.

DIGITAL-CONTROLLED BRIDGELESS PFC

Among other bridgeless PFC topologies [1] [2], Fig. 1 is an example of a bridgeless PFC which has been widely adopted by the industry. It has two DC/DC boost circuits [3] [4], one consists of L1, D1 and S1, while the other consists of L2, D2 and S2. The D3 and D4 are slow recovery diodes. The input AC voltage is measured by separately sensing the line and neutral voltages with referencing to internal power ground. By comparing the sensed line and neutral signals, the firmware knows whether this is a positive half-cycle or a negative half-cycle. During a positive half-cycle, the first DC/DC boost circuit, L1-S1-D1, is active and the boost current returns to AC neutral through diode D4. During a negative half-cycle, the second DC/DC boost circuit, L2-S2-D2, is active and the boost current returns to the AC line through diode D3. A digital controller like the UCD3020 is used to control this bridgeless PFC.

A bridgeless PFC essentially consists of two phase-boost circuits, but only one phase is active at any moment. Compared with conventional single-phase PFCs using the same power devices, the switching losses of a bridgeless PFC and a single-phase PFC should be the same. However, a bridgeless PFC current passes only one slow diode (D4 for positive half-cycle and D3 for negative half-cycle) instead of two at any time. Thus, the efficiency improvement relies on the conduction loss difference between one diode and two. Moreover, the bridgeless PFC efficiency can be further improved by turning the inactive switch on fully. For example, during a positive cycle, while S1 is controlled by the PWM signal, S2 can be fully turned on. Since the voltage drop on MOSFET S2 may be lower than diode D4 when the flowing current is below a certain value, the return current partially or totally flows through L1-D1-RL-S2-L2, and then back to the AC source. The conduction loss is decreased and the circuit efficiency can be improved, especially at light-load. Similarly, during a negative cycle, S1 is turned on fully while S2 is switching. The control waveform for S1 and S2 is shown in Fig. 2.

ADAPTIVE BUS VOLTAGE AND SWITCHING FREQUENCY CONTROL

Traditionally, efficiency is specified at full-load for both high-line and low-line. Now, most applications such as computing servers and telecommunications power require that efficiency at 10-50 percent load ranges, along with full-load, should all meet the standard's specifications. In most AC/DC applications, a system has a PFC and a down-stream DC/DC stage, so the efficiency is measured based on the whole system. To improve the whole system efficiency at light-load, one method is to reduce the PFC output voltage and switching frequency. This requires the awareness of load information, which is usually implemented by measuring the output current with extra circuits.

With digital controllers, however, these extra circuits are not necessary. With the same input AC voltage and DC output voltage, the output current is proportional to voltage loop output. So if we know the output of the voltage loop, we can adjust the frequency and output voltage accordingly. With digital controllers, the voltage loop is implemented by firmware, its output is already known, so it is easy to implement this feature, and the cost is much cheaper than using an analog approach.

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CURRENT SENSING THROUGH CURRENT TRANSFORMER

One difficulty of bridgeless PFC is how to sense a rectified AC current. As explained earlier, the AC return current (part or total) may flow through the inactive switch instead of the slow diode D3/D4. Therefore, to use a shunt in the ground path to sense the current, as with conventional PFC, is no longer applicable. Instead, a current transformer (CT) is used, one for each phase (Fig. 1). The outputs of these two current transformers are rectified and combined together to generate the current feed back signal. Since at any time only one current transformer has rectified output signal, even they are combined, there is only one feedback current signal at any time.

As shown in Figs. 3 and 4, because the current transformer is placed right above the switch, it only senses the switch current, which is only the rising part of the inductor current. For digital control implementation, this switch current signal is measured at the middle of PWM on time T_a. It is an instantaneous value, represented as I_sense in Figs. 3 and 4. The measured switching current I_sense is equal to the average PFC inductor current only when the current is continuous (Fig. 3). When the current becomes discontinuous as shown in Fig. 4, I_sense is not equal to the average PFC inductor current any longer. In order to compute the inductor average current, the relationship between the middle point sensing current I_sense and the average inductor current over a switching period should be built and be applicable for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM).

For a boost-type converter in steady state operation, the second voltage of the boost inductor should maintain balance in each switching period:

T_a × V_IN = T_b × (V_O - V_IN) (1)

Where:

T_a = Current rise time (PWM on time)

T_b = Current fall time (PWM off time)

V_IN = Input voltage

V_O = Output voltage, assuming all power devices are ideal.

From Figs. 3 and 4, we can calculate the inductor average current I_ave in terms of I_sense:

Where T = Switching period.

Combining Equations (1) and (2) together, we get:

Through Equation (3), the average inductor current I_ave is interpreted in an instantaneous switch current I_sense. I_ave, which is the desired current and I_sense is the current reference for current control loop. The real instantaneous switch current is sensed and compared with this reference, the error is sent to a fast error ADC (EADC), and finally the digitized error signal is sent to a digital compensator to close the current control loop.

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DYNAMIC ADJUST LOOP COMPENSATOR

Total harmonic distortion (THD) and power factor (PF) are two very important criteria for judging PFC performance. A good loop compensator should have good THD and PF. However, since the input range of PFC is so wide, it can extend from 80 Vac to as high as 265 Vac. A compensator having a good performance at low-line may not work well at high-line.

The best way to do this is to adjust the loop compensator based on the input voltage accordingly. The digital compensator in the UCD3020 is a digital filter consisting of a second-order infinite-impulse-response (IIR) filter cascaded with a first-order IIR filter. The control parameters, the so-called coefficients, are saved in a set of registers. This register set is called a bank. There are two such banks and each can store different coefficients. Only one bank of coefficients is active and used for the compensation calculation, while the other bank is inactive. The firmware can always load new coefficients to the inactive bank. During the PFC operation, the coefficient banks can be swapped at any time to allow the compensator to use different control parameters for a different operation condition.

IMPROVING PF AT LIGHT-LOAD

With this flexibility, we can store two different coefficient sets (one for low-line, one for high-line), and swap the coefficients based on input voltage. The loop bandwidth, phase margin and gain margin can be optimized at both low-line and high-line. This dynamically adjusting control loop coefficients, along with using firmware to compensate the possible offset of the current transformer, greatly improve THD and PF. Figs. 5 and 6 are testing results based on an 1100W bridgeless PFC, the THD is as low as 2.23 percent at low-line and 2.27 percent at high-line, and PFs are 0.998 and 0.996 respectively.

Every PFC has an electromagnetic interference (EMI) filter at the input end. The X capacitors of the EMI filter will cause the AC input current leading AC voltage, which affects PF. This situation gets worse at light-load and high-line. The PF will be difficult to meet a rigorous specification. To increase the PF at light-load, we need to force the current to delay accordingly. How can we achieve this?

We know that PFC current control loop is trying to force the current to match its reference. The reference is basically the AC voltage signal, with a different magnitude. So, if we can delay the voltage sensing signal and use the delayed voltage signal for current reference generation, the current can be delayed to match the AC voltage signal, thus the PF is improved.

First, the input AC voltage is measured through the ADC. Firmware reads the measured voltage signal, adds some delay, and then uses the delayed signal to generate the current reference. A testing result on an 1100W bridgeless PFC is shown in Figs. 7 and 8. In this test, V_IN = 220V, V_OUT = 360V, and load = 108W (about 10 percent of full load). Channel 1 is I_IN, channel 2 is V_IN, and channel 4 is the measured V_IN signal with delay. In Fig. 7, no delay was added on measured V_IN, PF = 0.86, THD = 8.8%. In Fig. 8, measured V_IN signal was delayed by 300us and PF is improved to 0.90. Further PF improvement is possible, but at the cost of THD since further delaying the current reference results in more current distortion at AC voltage crossover points. In Fig. 9, the measured V_IN was delayed by 500us and PF is improved to 0.92. However, the current was distorted at the voltage crossover point. As a fact of result, THD worsens to 11.3%.

NONLINEAR CONTROL

The voltage loop control is less complicated versus current loop. For a digital implementation, the output voltage V_O is sensed by an ADC, then compared with a voltage reference. A simple proportional-integral (PI) controller can be used to close the loop.

Where:

U = Control output

Kp = Proportional gain

Ki = Integral gain

E[n] = DC output voltage error sample

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As mentioned above, one benefit of using digital control is that it can do non-linear control. To improve transient response, a non-linear PI control can be used. Fig. 10 shows an example of a non-linear PI control. When error is bigger, which usually happens at transient, a bigger Kp gain is used. This speeds up the loop response when the error exceeds set limit and the recovery time is reduced. For an integrator, it is a different scenario. It is well known that the integrator is used to eliminate steady state error. However, it often causes saturation problems and its 90 degree phase lag also affects system stability. For these reasons, a non-linear integral gain ^[5] is used (Fig. 10). The integral gain, Ki, reduces when error exceeds a certain level to prevent saturation, overshoot, and instability.

Another advantage of digital voltage loop control is called integrator anti-windup. This usually happens at AC drop. When AC drop occurs and the downstream load continues to draw current, the DC output voltage starts to descend, but PFC control loop still tries to regulate its output. Once AC recovers, the saturated integrator may cause the DC output voltage to overshoot. To prevent this, the firmware can reset the integrator as soon as it detects AC recovery, and DC output reaches its regulation point.

REFERENCES

1. Slobodan Cuk, “True Bridgeless PFC Converter Achieves Over 98% Efficiency, 0.999 Power Factor,” Power Electronics Technology, July 2010.

2. Laszlo Huber, Yungtaek Jang, and Milan M. Jovanovic, “Performance Evaluation of Bridgeless PFC Boost Rectifiers,” IEEE, 2007.

3. A.F. Souza and I. Barbi, “High power factor rectifier with reduced conduction and commutation losses,” International Telecommunication Energy Conf. (INTELEC) Proc., Session 8, Paper 1, Jun. 1999.

4. T. Ernö and M. Frisch, “Second generation of PFC solutions,” Power Electronics Europe, Issue 7, pp. 33-35, 2004.

5. Zhiqiang Gao, “From linear to non-linear control means: a practical progression,” ISA Transactions, Vol. 41, No. 2 p. 177-89, April 2002.

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