Power Budgets—Don’t Forget The Memory

May 1, 2004
As memory begins to dominate SoC, Jud Bond looks at the contribution of memory power to the system’s power budget.

With the increasingly larger amounts of memory deployed in low power applications, it is critical to apply power-saving techniques to the memory in order to achieve system power goals. Three key elements need addressing: the embedding of system memory into the SoC, memory technology options that affect both active and standby power and dynamic power management techniques.

TO EMBED OR NOT TO EMBED? Embedding the system memory has significant system power implications over external memory solutions. Too often power budgets are allocated on a per-chip basis, without regard to total system power.

Consider an embedded system with an SoC-based processor and 4Mbit (64Kx32) memory. The memory interface consists of 32 data lines and 20 assorted address and control lines. Assuming that one-half of the signals are transitioning at any one time, a total of 26 signals need to be accounted for in terms of power. Each of these signals has an effective loading of 8-10pF, based on the following breakdowns:

  • 4 pF – output driver including ESD protection
  • 1pF – output pad
  • 2pF – input buffer including ESD protection
  • 1pF – input pad
  • >2pF – leadframe + PCB trace.

Power distribution is calculated as 1/2CV2. Assuming that I/O voltage is 2.5V and that the memory is operating at 100MHz, the I/O power consumed in performing memory operations would equal approximately 81mA. Therefore, today's power requirements heavily favour the embedding of system memory.

ACTIVE AND STANDBY POWER Active power is the power consumed by the memory and its interface when being accessed for a read or a write. Standby power is the power consumed by the memory when the stored value is being retained, but not accessed. Each technology (six transistor and one transistor, one capacitor) has different characteristics concerning active and standby power.

Traditionally, active power was considered of lesser importance in the power budget due to the relatively short time the device was active as compared to the time it was in standby mode. Today's applications depend on many new features that require a greater percentage of the time being in active mode. For example a 2G handset's functionality consisted mainly in the call and call management functions associated with wireless communication. Typically a 2Mb SRAM was sufficient for protocol stack, menu system and scratchpad. By contrast, today's 3G phones, in addition to voice services, support a wide variety of options such as data services, web browsers, audio players and MPEG-4 video. These handsets can easily require up to 16Mb of SRAM.

The 6T memory cell, which is a latched structure, dissipates the highest active power because of the latch action and the inherent size of the cell. In addition, large 6T arrays typically contain long metal lines that create high node capacitance increasing the power drain. By contrast, 1T1C memories read and write data by charging or discharging the capacitor in the memory cell. The small size of the 1T1C cell results in shorter metal line lengths and lower node capacitance that translate to lower power.

Standby power is still the mark by which low power and wireless applications are measured. Battery life is directly related to the efficiency of the system's standby power. In past generations, standby power in memory was not given major consideration due to the performance of 6T-SRAM in standby mode. The latched action of the 6T cell, coupled with the heavily oxided transistors of past processes resulted in a memory cell that consumed little power in a standby mode as compared to other system elements. With the advent of very-fine geometry processes (0.13micron and finer), this picture has changed greatly. While benefiting from the speed and density afforded by ever shrinking geometries and supply voltages, the industry is facing a power crisis brought about by these same processes. The issue of leakage current, while always present in previous silicon generations, has become an overriding concern to the design industry.

Leakage current is simply defined as the uncontrolled (parasitic\} current flowing across regions of the semiconductor structure in which no current should be flowing. It can be composed of several elements: sub-threshold leakage current, gate direct leakage tunneling current and source/drain junction leakage current. The ITRS has published its Low Standby Power (LSP) Logic Technology Requirements for both the near and long term, which include leakage current requirements. It is generally acknowledged these leakage requirements cannot be met with current methodologies. In fact it is estimated that leakage current will increase on the average 7.5X with each chip generation. It is no longer valid to assume that gate-leakage is an insignificant contributor to standby power in embedded memory.

Each memory technology approaches standby power differently. 6T memory, because of the basic structure of the 6T cell, is very susceptible to leakage. In its standby state, the 6T memory cell has four separate leakage paths in which current flows. 6T leakage in 0.13micron and below results in a significantly higher standby current than an equivalent 6T memory array in 0.18micron or higher. While circuit techniques are constantly being employed to improve 6T leakage, standby current will always suffer with a six-transistor design in advanced processes. 1T1C memory cells such as embedded DRAM and MoSys' 1T-SRAM do not suffer the same leakage effects. The basic structure of the 1T1C cell contains only a single leakage path in standby mode. In addition, the relative smaller cell results in overall lower leakage. While it is true that 1T1C cells require a refresh current to maintain memory state in standby, design techniques have reduced this current to such an extent that refresh current is often significantly less than the leakage current of an equivalent 6T memory array.

DYNAMIC POWER CONTROL Traditional low power design techniques include reducing voltage and frequency, clock control, transition minimisation, and selective sleep or power down. Early implementations of power-saving design methods were mainly static in nature, ie a reduced voltage or frequency was constantly applied to the system resulting in a constant savings that was not dependant on true system activity or throughput requirements. While power savings were realised, often the results were not optimal. Recent advances, such as dynamic clock control, adaptive voltage and frequency scaling and selective sleep or shutdown are implemented as a dynamic control, and allow the designer to maximise power savings in relation to system load and throughput. In other words, for maximum power savings, power saving design techniques must be applied dynamically to compensate for system activity and throughput requirements.

Until recently, most low power design techniques have been targeted to reduce the power of the logic circuits. With the increased amount of embedded memory in low power systems, these same design techniques must also be applied to the memory in order to achieve system power goals. A good example of this is the 'sleep' mode employed by many systems.

During periods of inactivity it is traditional to put the processor in a 'sleep' or standby state to reduce power. This can be accomplished by software, clock control, or other methods. With very large embedded memories in fine geometry processes, this is not the case.

In the case of 6T memory, leakage current can exceed the very logic current that one hopes to save by sleeping the logic. In the case of 1T1C memory, the refresh requirements are still present and will consume power. Clearly, in order to conserve power, the memory must be made aware of the 'sleep' or standby condition allowing the memory to operate in a 'power optimised'mode. An example of this is the low-power standby mode of MoSys' 1T-SRAM, which reduces standby current by an order of magnitude.

To assist designers in dealing with the problems of leakage encountered in leading edge processes, MoSys has developed a family of low-leakage embedded memories.

1T-SRAM-M technology addresses the requirements of large memories in low power applications. Applicable in memory sizes of 0.5Mbit and greater, 1T-SRAM-M employs the same one transistor, one capacitor bit-cell used in previous generations that allows very high memory density to be achieved. In addition to the already low active power inherent with 1T-SRAM, the 1T-SRAM-M exhibits only one quarter the standby power (leakage) than 6T memory.

The 1T-SRAM-M technology is available with the 'Q' option that offers memory densities up to four times that of large 6T memories, while maintaining the low-leakage characteristics of 1T-SRAM-M. All 1T-SRAM-M memories come with integral Transparent Error Correction (TEC). This offers dynamic data repair at no penalty to speed or area.

For small, low-leakage memories (0.5Mbit and below) there is the 6T-SRAM-R range. This technology borrows leakage reduction techniques from previous MoSys memory technologies and applies them to a 6T design resulting in a memory that exhibits 50% the leakage of competitive 6T memories. As with the 1T-SRAM-M technology, the MoSys 6T-SRAM technology contains TEC for reliability and elimination of fused redundancy.

See associated figure

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