Power-Over-Ethernet Chips Give LANs A New Outlet

Oct. 13, 2003
If you've grown accustomed to viewing the familiar LAN connector as a data port, think again. That RJ-45 jack makes a great power outlet. At least that's the message being promoted these days by Power-over-Ethernet (PoE) proponents. They want...

If you've grown accustomed to viewing the familiar LAN connector as a data port, think again. That RJ-45 jack makes a great power outlet. At least that's the message being promoted these days by Power-over-Ethernet (PoE) proponents. They want equipment designers of every ilk to know that standard CAT 5 unshielded twisted-pair cabling makes a great medium for transmitting dc power, along with the usual data, to network peripherals. Although this concept grew out of a need to eliminate the power adapter required by voice-over-IP (VoIP) phones, PoE technology has broad implications well beyond the phones. As a consequence, manufacturers of power semiconductors are currently gearing up development and production of numerous PoE control chips.

These control chips will help designers of networking hardware and network peripherals to realize the many benefits of PoE. One advantage is reliability. With power emanating from a central point on the LAN, the 48-V power source can be backed up by a UPS, ensuring a higher degree of reliability for peripherals than those operating off the ac grid. That feature is critical to VoIP phones, because users expect these devices to have similar reliability to traditional POTS phones, which have always operated off a battery-backed power source.

Another PoE advantage is convenience. Peripherals only need one chord for plugging into the LAN, so the requirement for an ac-dc adapter is eliminated. Even more compelling may be the ability to place peripherals in spots that currently have no ac outlets. Peripherals such as WLAN access points and security cameras can be located in ceilings and other remote sites without running ac power cabling, which require the services of an electrician (Fig. 1).

However, another PoE benefit may be even more compelling. With the emergence of 802.3af as a global standard, the LAN outlet becomes a universal power jack. As Igal Rotem, CEO of PowerDsine, observes, "The \[PoE-enabled\] RJ-45 is the only standard power connector in the world."

That gives a PoE power supply a capability not offered by power supplies with universal, 85- to 265-V ac input ranges. Although the latter can accommodate all commonly encountered line voltages, they still require different plugs to mate with all of the various power jacks. In contrast, the PoE-powered device will operate anywhere using the same RJ-45 connector. Of course, the caveat is the limit on available power. The new IEEE 802.3af PoE standard only allows a powered device to draw up to 12.95 W.

Nevertheless, that level is sufficient for a variety of products, including battery chargers for portable devices such as cell phones, PDAs, and notebooks. Moreover, PC vendors are said to be developing low-power notebooks that can be powered directly off the PoE port.

Other possible power devices (PDs) include factory automation equipment, RF ID scanners, security systems, time card systems, credit card terminals, and keyless entry systems. One of the more exotic applications is Gibson Guitar's use of the LAN to transmit digitized audio from the guitar back to a PC. In this application, getting rid of the ac power chord with PoE improved the SNR of the audio, in turn lowering bit error rates. This benefit could be extended to other areas of data acquisition.

Efforts to develop PoE equipment and components were given a boost last June when the IEEE 802.3af-2003 PoE standard was formally ratified, establishing uniform requirements for managing and distributing 48-V dc power over the LAN. That standard defines the protocols for the power-sourcing equipment (PSE), the Ethernet hubs and switches, to transmit power over CAT 5 and other cabling to the PDs, such as the VoIP phones and other network peripherals.

The PSE encompasses two categories of equipment: midspan and endspan devices. A midspan device is a standalone unit that adds the PoE capability to existing networking equipment. The unit is inserted into the LAN between the Ethernet switch and the peripherals. However, a midspan device requires additional cabling, takes up extra space, and adds cost to the system. These problems are lessened by incorporating PoE functionality directly into the Ethernet switches. Such pieces of equipment are called endspan devices.

Today, semiconductor vendors are doing their part to craft power-management ICs that implement the functions needed to build IEEE802.3af-compliant PSE and PDs. Although the most recently developed PoE chips aren't the first chips aimed at this application, they generally offer higher levels of functional integration than their predecessors. By increasing the level of integration, these components reduce the cost and development effort associated with adding PoE capabilities to network equipment and peripherals.

Naturally, PoE chip development is an ongoing, industry-wide effort with promises from vendors that the chips to come will offer even more integration, smaller size, and lower cost. In the meantime, semiconductor vendors with PoE offerings are tackling the pressing system design issues, such as the need for compatibility with legacy systems.

SEMICONDUCTOR DEVELOPMENTS This year, several semiconductor vendors introduced power-management ICs for PoE applications. Typically labeled as power managers or power controllers, these chips are essentially hot-swap controllers with additional circuitry to perform the PSE and PD operations defined by IEEE 802.3af.

The PSE power managers perform PD detection (discovery) and classification of PD power level, as well as control the application and removal of power to the PD. In the detection mode, the PSE power manager looks for the 25-kΩ signature that distinguishes a PD from a data-only peripheral. In this case, the chip applies a pair of relatively low voltages (less than 10 V) to the port in question, measures the current, and then calculates the voltage-versus-current slope to determine if the required resistance was detected. Detection is an important step because it ensures that the PSE won't apply 48 V to a data-only peripheral.

After PD detection, the PSE looks for a classification signature on the PD that identifies its power consumption. Power classification is an option in the IEEE standard that allows PDs to be grouped into one of three power classes. The power limits for these classes are 3.84 W (Class 1), 6.49 W (Class 2), and 12.95 W (Class 3). When a device doesn't present a classification signature, it's assumed to draw the maximum 12.95 W and is designated as Class 0 (Fig. 2).

The PSE tests for a classification signature by applying 15.5 to 20 V to the port, measuring the current drawn, and then integrating. Afterward, the PD is assigned to one of the three classes, depending on the measured current level. Each class has a range of measured currents for classification, and these ranges are different from the class's current limits in operation.

By gathering classification data on all of the PDs connected to the LAN, the PSE enables the host controller to calculate worst-case power draw to ensure that a PD will never be cut off.

The PSE power managers also implement current-limiting and other forms of fault protection. The IEEE standard establishes two current limits. The PD may draw up to 350 mA continuously (the lower limit) or up to 400 mA (the upper limit) for 50 ms. The latter limit allows for transients. When the PD current rises above a certain threshold (set somewhere between 400 and 450 mA, typically 425 mA), the PSE must limit current to the PD (Fig. 3).

Under the dc disconnect scheme, a minimum current requirement is also imposed. If the PD current consumption falls below a low-current threshold (set somewhere in the 5- to 10-mA range), it's assumed that the PD has been disconnected and the PSE removes its power.

With the IEEE standard, the PSE can opt for either the dc disconnect method or an ac disconnect method. The latter method, which is considered somewhat less robust and more subject to interference, was developed as a means of avoiding patent-infringement issues. The dc disconnect method became the subject of some pending litigation. The ac disconnect method is viewed by some as a short-term solution until legal issues are resolved. Once that clears, equipment manufacturers should be free to use the dc disconnect scheme.

The PSE-side power managers introduced to date can perform the PD detection, classification, and current limiting functions in a single chip with some external passives. In most cases, the power-manager ICs also incorporate gate drivers to control application of the 48-V dc to each port using external MOSFETs.

Although the IEEE standard defines a set of basic requirements that drive the development of PoE power managers, vendors take different approaches to implementing these requirements, while also providing other options. For example, PSE-side power managers differ by the number of ports they can manage per chip.

They also provide disparate control methods. For instance, some rely on a host-based control, while others allow for autonomous or semi-autonomous operation. Some chips implement the dc disconnect method to sense a disconnected PD, while others give the option of using ac disconnect.

Meanwhile, the PD-side power managers typically present the 25-kΩ signature resistance and allow the PD to be programmed for a power classification signature. Unlike with the PSE power managers, an on-chip power MOSFET is generally included in the PD power managers for switching the 48-V power rail. Other special functions are inrush current limiting, the ability to switch out the signature resistance during operation, and power-good output (see the table).

Last year, PowerDsine introduced its second generation, power-over-LAN solution for the PSE. Its PD64008 driver ASIC offered eight-port PSE control designed for compliance with IEEE 802.3af. The company also offered the the PS64009, an add-on controller that enables the system designer to implement functions beyond what the IEEE requires. This year, Linear Technology, Maxim Integrated Products, and Texas Instruments also introduced PSE power managers designed for compliance with IEEE 802.3af. The parts from TI and Linear were part of power-management chip sets that also included PD power managers, enabling full PoE system development. TI introduced its TPS2383 octal PSE power manager and its TPS2370 power interface switch for PoE powered devices. Linear announced its LTC4258/59 quad PoE controller and its LTC4257 PoE interface controller for powered devices.

Maxim Integrated Products also introduced a PSE power manager, the MAX5922A/B/C, a +48-V, single-port network power switch for power over LAN. Note that this part differs from other PSE power managers by the number of ports it controls (one port rather than four or eight) and in its switching of the positive supply rail rather than the negative rail. More recently, the company announced the MAX5935, a quad network power controller with ac disconnect. The company plans to introduce its MAX5940A/B PoE interface controller for PDs shortly.

When combined with other data-handling and control components, these various PoE power managers enable development of IEEE-compliant networking systems and peripherals (For a generalized schematic of PoE power managers in the application, see the online figure.

Note that when a midspan device is used, the dc power must be transmitted over the spare pairs of the LAN. When the PSE is an endspan device, it typically transmits power via the data pairs. Use of diode bridges on the PD allows it to accept power with the proper polarity from either the spare pairs or the data pairs.

Although compliance with IEEE 802.3af is a must for new PoE equipment both now and in the long run, compatibility with legacy PoE systems is an important short-term concern. The two main legacy systems belong to Cisco and PowerDsine.

In the Cisco system, the Ethernet PHY uses the differential datapath to perform PD detection using a loopback scheme. Here, the absence of a link pulse (part of the Ethernet data scheme) is used to detect PD disconnect. Existing 802.3af-compliant PSE solutions can be adapted to work with Cisco PDs (mainly VoIP phones) with some workarounds. The PSE must be configured so that the PHY (network physical-layer interface ICs) signals when the power manager should apply and remove dc power to the PD.

On the PD side, inrush currents are an issue because some legacy systems use a lower current limit than the IEEE standard. If a large input capacitor is present on the PD, the full IEEE inrush current may be required by the device. In some legacy systems, the PSE would identify this current level as a fault and shut down power to the PD.

One vendor, Linear Technology, offers a variation on its PD-side power manager (LTC4257-1), which turns on initially with the lower inrush current limit and then reverts to the higher IEEE limit, allowing the PD to work with either legacy or IEEE-802.3af systems. TI, on the other hand, has a programmable inrush current limit, which addresses the same issue.

The legacy system developed by PowerDsine employs a large capacitor (47 to 470 µF) as the PD signature. This system isn't compatible with the IEEE system in the sense that a legacy PowerDsine system won't accept the IEEE signature and vice versa. However, as with the other compatibility issues, vendors generally develop solutions that accommodate the legacy systems.

IN DEVELOPMENT Most efforts to develop power-management ICs for PoE focus on the related tasks of integration and cost reduction. Integration relates not only to bringing on-chip the various functions needed for PoE tasks, but also to finding ways to better partition related power-management and data-handling functions. Also being pursued is a reduction in the cost per port when adding PoE to a piece of networking hardware.

PowerDsine is working with Motorola to produce a PSE-side power manager that will push integration to new levels by exploiting the capabilities of Motorola's SmartMOS8. This semiconductor process was selected for its ability to integrate FETs on silicon rated for up to 80 V and its ability to withstand inrush currents and thermals. On top of that, the device integrates large portions of digital circuitry (tens of thousands of gates). SmartMOS8 was originally developed for and deployed in automotive applications where some of these same characteristics are required.

The PowerDsine/Motorola ASIC now in development will integrate a high-voltage MOSFET switch together with high-voltage mixed-signal circuitry, digital control, and communications. According to the vendor, existing designs for a 48-port Ethernet switch now require more than 1200 components. But using the new ASIC, this number will be reduced to 192 parts or just four parts per port. First samples of this chip are expected by the end of the year.

Most semiconductor vendors embarking on PoE chip development enter with a general background in power management and some particular experience with hot-swap control. However, there are vendors looking to join the field by exploiting their expertise in other, PoE-related areas. For example, National Semiconductor's and Micrel Semiconductor's portfolios include both power-management components and PHYs. For these companies, the goal now isn't to fully integrate the PHY and power-management circuitry. Rather, it's to develop chip sets that will achieve the most useful and cost-effective partitioning and integration of data and power-management functions at the system level.

National Semiconductor is currently developing PSE and PD-side power managers. Integration and partitioning drive development on the PSE side. On the PD side, its chip development is driven by requirements for integration and flexibility. The company expects to produce first silicon about a year from now.

Meanwhile, Micrel plans to introduce a PSE-side chip set with both PHY and power-management functions in the second half of 2004. The chip set will offer an enhanced set of system-level features while lowering overall cost per port. During this time, Micrel is also expected to unveil a PD-side power manager that will integrate a switching regulator for stepdown dc-dc conversion of the 48-V power supply.

Another vendor, Semtech, plans to introduce PSE and PD power controllers as part of a turnkey power-management solution for PoE. In this case, the controllers will complement the company's switching regulators, PWM controllers, and LDOs, which will step down the 48-V dc bus to lower chip-level voltages. Note that other vendors mentioned in this report also offer these types of components. Although a discussion of these ICs is beyond the scope of this article, their performance will certainly be significant for system designers developing PSE and PDs.

For example, the efficiency of stepdown regulators will be a key consideration for some applications given the limited power available to the PDs. Moreover, the task of stepping down the 48-V bus is made more difficult because the PDs are likely to require multiple supply voltages.

Most of the PSE controllers introduced so far provide multiport control. These devices rely on external MOSFET power switches and current sensing resistors. However, chip vendor Supertex plans to offer an alternative to these "ganged" controllers. Supertex describes its first offering as an "n-port distributed PSE" controller. This device provides complete IEEE802.3af functionality for each port, but it also includes an on-chip power switch as well as EEPROM and an I2C interface to store various device parameters and measure operating points.

The company claims that taking a distributed control approach (putting a controller at every port) reduces wiring requirements, saving board space and lowering crosstalk versus that of centralized control schemes based on ganged controllers.

At the same time, this approach enables accurate thermal monitoring of each power switch. In addition, a 100-V rated on-chip regulator will allow the controller to operate directly from the 48-V supply, eliminating external shunt components. This device is slated for introduction in the first quarter of 2004. Following that release, Supertex plans to introduce a device that can serve as either a PD or PSE controller.

BEYOND CHIPS Much of the focus now is on optimizing the chips and chip-set solutions, yet packaging also plays an important role, particularly as it relates to the integration of magnetic and passive components. In recent years, connector vendors have begun to take the magnetics, capacitors, and resistors used for isolation and signal integrity in Ethernet applications and integrate them into the RJ-45 jack.

According to Molex, the next step will be to integrate the PSE power-management IC into the RJ-45. To this end, the company is working closely with a semiconductor vendor to develop such a connector. It's slated to debut in mid-2004.

Beyond the component-level efforts, which include development of magnetics, circuit protection, and other passives, power-supply companies are working to develop PoE-tailored ac-dc and dc-dc power supplies. (For more on power supply developments, see the Analog and Power Techview in this issue, p. 26.)

Need More Information?
Fairchild Semiconductor
Madhu Rayabhari
[email protected]

Linear Technology Corp.
David Dwelley
[email protected]

Maxim Integrated Products
Harmik Singh
[email protected]
(408) 737-7600; www.maxim-ic.com

Micrel Semiconductor
Adolfo Garcia
[email protected]

Wolfgang Hermann
[email protected]

National Semiconductor
Paul Greenland
[email protected]
(408) 721-3210; www.national.com

Igal Rotem
[email protected]
+972-9-7755102; www.powerdsine.com

George Georgalis
[email protected]
(805) 480-2176; www.semtech.com

Brian Hedayati
[email protected]

(408) 222-8888; www.supertex.com

Texas Instruments
Steven Hemmah
[email protected]


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