The gate-leakage problem does indeed have hope, some of which has already arrived in the form of high-k dielectrics. Based on alloys of hafnium, such materials have been rolled out by Intel for its 45-nm generation of products expected to be shipped by the end of this year. IBM will follow suit with its own variation on high-k dielectrics early in 2008.
High-k (or high dielectric-constant) gate insulators will aid in the struggle against leakage by virtue of the fact that they can be physically thicker without degrading performance.
Other materials advances, including strained silicon and silicon-on-insulator technologies, offer some performance gains but don't directly address gate leakage. However, one startup has made progress toward enhancing the electrical properties of existing materials used in existing bulk-CMOS processes to get leakage under control.
Robert Mears, founder of Mears Technology, describes his company's MST technology for CMOS as one that makes relatively simple changes to silicon. "We can modify its properties so that it becomes inherently anisotropic," explains Mears. "As a result, it becomes more conductive in the plane and less conductive out to the plane."
MST technology involves a film that acts as a channel-replacement technology, sitting directly below the gate dielectric. This film's anisotropic properties enhance current flow from source to drain, providing higher mobility so IDsat is improved and drive current is higher. At the same time, the gate leakage is reduced without increasing the thickness of the gate oxide.
"Gate leakage is a quantum mechanical tunneling problem," says Mears. In terms of electron tunneling, the gate oxide can be seen as a barrier. The ability of electrons to transgress that barrier can likewise be thought of in terms of an impedance-matching issue. MST technology effectively creates a mismatch that prevents electron tunneling without affecting the barrier's physical dimensions.
Ultimately, the answer to solving the leakage problem lies in a combination of various design techniques combined with process advances like FinFETs, the Mears technology, and high-k dielectrics. Until the materials technologies go mainstream at 45 nm and beyond to squelch gate leakage, though, designers must continue to rely on design smarts to subdue subthreshold leakage.