Athyristor switch typically is used when controlling power in the kilowatt range. In a thyristor, the output power is controlled by controlling the time (or phase angle) during which the thyristor remains “closed” in a conduction cycle. To control phase-angle firing, the circuit must be able to detect when the line voltage crosses zero, and then determine how long to wait before firing a control element in each half cycle.
The digitally controlled phase-angle firing circuit described here generates an ac mains synchronous clock of 4096*2*ac main frequency. At the start of every half cycle of ac power, a set of counters running at 4096*2*ac power frequency counts a 12-bit number. At the end of the count, a triac is fired. The 12-bit number is output through the data port of the parallel printer adapter. Because the data port is only 8 bits wide, data is written in two steps and a “buffer” data layer is introduced to transfer the entire 12 bits in one step to the counters.
Looking at the circuit diagram of the timer, a 1-kΩ resistor and two diodes produce an ac mains synchronous square wave clipped to 0-5 V (Fig. 1). A positive differentiator is created by an RC network around inverters I1(A) and I1(B). These inverters produce a spike at every zero crossing of ac mains. Inverter I1(C) sums these two spikes to create a pulse at every zero crossing of the ac line voltage. The clock frequency appearing at the output of I1(C) is 2*ac line frequency. In our case, this frequency is 100 Hz, with the ac mains frequency being 50 Hz. Since a 12-bit controller is desired, every half cycle of ac mains should be marked with 4096 points. This is accomplished by multiplying 4096 with an ac mains synchronous 100-Hz signal using the phase-locked loop PL. The 100*4096-Hz clock is fed to counter C1, C2, and C3.
The diagram of the data multiplexer shows that the PC printer port is connected to two octal transparent latches (LS373), and the respective latch is selected by two bits of the control port (Fig. 2). The circuit works as follows: A 12-bit signal is divided into two parts, one 8-bit-wide LSB and the other 4-bit MSBs. The eight LSB bits are written to latch L1, and four MSBs to L2. To transfer the complete 12-bit word to the counter in one pass, two layers of latches¾one layer comprised of latches L1 and L2 and the other L3 and L4¾are introduced. The ac-line synchronous 100-Hz signal is used to transfer data from latch L1/L2 to latch L3/L4. After some delay, introduced by timer T1, this signal also is used to load counters C1, C2, and C3. At the end of the countdown, the carry output “fires” the triac.
