In multiple-output-voltage power supplies, the topology may place restrictions on the startup sequence. This can be particularly troublesome in an isolated power supply, where a lower output voltage must be present before a higher output voltage. Typically, the higher voltage is the source of power for the lower voltage output. Consider a system with an isolated 48-V input supply with a 3.3-V/9-A output and a 1.8-V/3-A output. The 1.8-V output must be present at the load before the 3.3 V is supplied to the load but regulates its power from the 3.3-V output voltage.
A straightforward approach generates something greater than 3.3 V (e.g., 5 V) with an isolated supply and generates the 3.3- and 1.8-V outputs with two buck regulators. Most synchronous buck controllers have Enable and Power Good functions that simplify the sequencing of the two outputs. For example, the Power Good pin of a TPS54310 (generating the 1.8-V output) can be tied directly to the Enable pin of a TPS54910 (generating the 3.3-V output). However, if the intermediate 5-V bus isn't used by anything else in the system, the double conversion of 48 V to 5 V, and 5 V to 3.3 V and 1.8 V generates unnecessary losses.
A second, more efficient approach generates the 3.3 V directly with an isolated supply, then generates the 1.8-V output with a single synchronous buck controller. A MOSFET can then be used to switch the 3.3-V output to the load after the 1.8-V output reaches regulation. A p-channel MOSFET may be an acceptable choice when the switched output doesn't draw much current. However, in higher-current applications, the lower cost of an equivalent n-channel MOSFET makes it a much more appealing option. Because an n-channel MOSFET requires a positive gate voltage to turn on, a voltage higher than 3.3 V must be present to enable the 3.3-V output.
The circuit in Figure 1 takes advantage of the 1.8-V power supply to provide a delayed Enable for the 3.3-V MOSFET. Synchronous buck controllers use a bootstrap circuit to drive the high-side MOSFET. They charge a bootstrap capacitor (C1) when the switch node is low and use this voltage to enhance a high-side MOSFET.
C1 peak charges C2 to approximately twice the input voltage through the internal bootstrap circuit and external diode (D1). The Power Good pin holds the switched MOSFET (Q1) off until the 1.8-V output reaches 90% of its steady-state value. The gate of Q1 then slowly charges through R1 and C3. The 3.3-V rise time can be adjusted by changing the time constant of R1 and C3. In addition to a low on-resistance, MOSFET Q1 needs a 2.5-V turn-on threshold to ensure that it's fully enabled by this circuit. Typical startup waveforms for this circuit are shown in Figure 2.
