Could This “2D” Transistor Process Transform Logic and Power Device Production?

CDimension recently unveiled a technology that enables conventional semiconductor fabs to use ultra-thin semiconductor materials to manufacture vertically integrated arrays of extremely small, fast, and efficient “2D” transistors. It has the potential to change what’s possible for both digital and power devices.

According to the company, it’s already helping several chipmakers explore how to apply their technology to produce digital and analog ICs that offer dramatically higher logic densities, operating speeds, and energy efficiency.

CDimension is also providing developers with resources that will eventually enable them to use the same process to produce vertically integrated chips that unify compute, memory, and power functions within a single, high-efficiency device.

BEOL Process Enables Atomically Thin Film Growth

At the core of the company’s commercial debut is a proprietary, low-temperature, back-end-of-line (BEOL) process, which enables the direct growth of highly uniform, atomically thin (6 nm/3 atoms thick) films of materials, such as molybdenum disulfide (MoS₂), onto a silicon substrate.

That layer can be processed using existing photolithographic processes to create transistors with much higher electron mobility (around 400 cm²/V/s), lower leakage and parasitic capacitance, and wider bandgaps (2.4 eV) than an equivalent CMOS device (Fig. 1).

Due to their thin structure and the absence of isolation wells, the resulting transistors also display significantly lower leakage and parasitic losses than their equivalent CMOS counterparts. As a result, internal testing of the so-called 2D devices fabricated in CDimension’s MoS₂ films have demonstrated up to a 1,000X improvement in transistor-level energy efficiency compared to silicon.

Moving From Lab to Fab

To help early adopters explore the technology, CDimension offers 4- and 8-in. silicon wafers with a MoS₂ film applied to them. Manufacturers can use these wafers to form 2D transistors using standard photolithographic processes available on most commercial 150- to 180-nm fab lines. This includes interconnects formed using a standard CMOS-compatible metallization layer such as copper. 

The short distances and low parasitics displayed by these interconnects contribute to the devices’ high performance. Even better ohmic contacts can be achieved with bismuth, antimony, and nickel, but using these would require additional process steps.

CDimension said that it expects early adopters will use these single-layer MoS₂-coated wafers to produce components such as low-power, high-speed MCUs, memories, and other digital devices. Other applications would be power devices that exhibit many of the advantages of wide-bandgap (WBG) materials such as gallium nitride (GaN) and silicon carbide (SiC).

Furthermore, the company noted that the technology has good potential for RF and sensing applications, and possibly quantum computing (with different materials).

A 3D Future?

Since the film deposition process is performed at 200°C, it can be used to create multiple layers of 2D devices and their associated interconnects without damaging the previously formed devices.

According to CDimension, this capability will eventually enable designers to create single-chip products that incorporate multiple layers of high-speed/low-power logic, memory, and other functionality, as well as high-density devices like MCUs with large, on-chip memories that are accessed through extremely short, low-resistance interconnects (Fig. 2).

When used to fabricate power devices, the resulting transistors can operate reliably at 40 to 45 V, are less susceptible to noise, and have switching speeds that are relatively voltage independent. CDimension said it’s confident that the channel length of these 1st-gen transistors can be adjusted to support higher voltages (100 V or less). Initial applications for 2D power devices could include high-efficiency, low-noise step-down regulators, especially for GPUs.

The first commercial applications for the technology are expected to hit the market in mid-2026, most likely small MCUs with integrated memory and power-management units (PMUs) for high-performance CPUs, GPUs, and SoCs.