Startup Puts Passives in the Package for AI Power Delivery

The AI boom is driving up the power demands of CPUs, GPUs, and other high-performance SoCs in data centers—and they show no signs of slowing down.

Today, the most advanced AI chips are bordered on virtually all sides by voltage regulators to convey the current over the last inch of the power-delivery network (PDN) into the point-of-load (POL). But in most cases, these chips are also surrounded by vast clusters of decoupling capacitors to smooth out the power rushing into these chips during rapidly changing loads. They act as local power reservoirs, storing and releasing current instantaneously to maintain a stable powe- supply voltage and minimize noise.

To keep the power as smooth and stable as possible, large bulk capacitors are placed in and around the voltage regulators to reduce noise or other fluctuations in the power supply at frequencies of tens of kilohertz.

The circuit board is also swarming with small, high-frequency capacitors, strategically placed close to the processor's power and ground pins to handle more rapid current fluctuations and prevent voltage drop. In most cases, these are multi-layer ceramic capacitors (MLCCs), located directly under the processor on the PCB to filter out noise in the range of tens of megahertz.

But, in the era of power-hungry AI chips, it's becoming increasingly difficult to place all of these passive components close enough to the processor to maintain optimal power integrity.

Saras Micro Devices aims to address the challenges of traditional power delivery with its Saras Tile, or STILE. The startup integrates capacitors into one of these tiles that can be embedded into the organic substrate of the processor's package.

By moving the power decoupling from the board to the package, the STILE brings the capacitors closer to the processor. This reduces the parasitic inductance and resistance that can impede power as it races into the load, improving both efficiency and performance of the PDN.

At the core of each STILE is the company's polymer aluminum solid electrolytic capacitor technology. Saras said it has the high capacitance density to remove "function-specific" devices in the system.

Instead of placing them around the processor on the PCB or embedding them inside the package one by one, Saras explained that it puts a wide range of passive components into a single "multifaceted" module that can handle a number of different power domains within high-performance chips. That reduces the number of separate capacitors and other passives used to supply them.

The company said its passive components can run at up to 10 MHz, complementing on-chip capacitors that will still handle high-frequency power filtering.

STILE: A New Approach to In-Package Power Delivery 

While all of the largest players in passive components are rolling out capacitors with smaller form factors and larger capacitance values, Saras is positioning STILE as a purpose-built solution for the AI era.

Today, high-performance AI chips, such as NVIDIA's latest Blackwell GPUs, are burning more than 1000 W to run computationally heavy workloads such as training and inference. A single one of these chips can have more than 100 billion transistors based on advanced process nodes like 5 nm and 3 nm, which inevitably leak more current and, as a result, waste power.

With the amount of power consumed by these chips rising to more than a kilowatt and the voltages used by the transistors sliding into the millivolt range, the situation is pushing the core power rail current to more than 2,000 A.

In general, these power-hungry SoCs are powered by a multiphase voltage regulator. These DC-DC converters are comprised of a number of modular power stages or "phases" responsible for delivering power as well as inductors and capacitors responsible for fine-tuning it before it enters the SoC. In a way, a multiphase DC-DC converter is the power equivalent of a multicore CPU: It spreads out the load current over several phases, allowing it to supply power faster, more efficiently, and more accurately.

The voltage regulator translates the 48-V DC output from the server’s power supply—or the 12-V DC output from the onboard intermediate bus converter (IBC)—to the tightly regulated voltage used by the processor.

In most cases, power blocks are placed as close as possible to the SoC in a configuration called "lateral power delivery." Power is conveyed from the voltage regulators to the processor over copper wires, resulting in significant power losses due to the resistance in the PCB. As currents rise to more than 1,000 A, these transmission losses are adding up.

As a result, engineers are rewiring everything for "vertical power delivery," relocating the voltage regulators under the processor on the other side of the PCB. The closer placement reduces the distance to the load and the resistance impeding the current.

Using its STILE technology, Saras said it can remove the capacitors under the board and replace them with one or more substrate-embedded passive modules, paving the way for vertical power delivery. To deliver power seamlessly to the processor above, the STILE technology features double-sided contacts, reducing the complexity of the PDN and enabling faster and more efficient high-current feeds.

Since each application is different, Saras said it works with customers to create custom STILEs, adapting the width, length, and thickness of the modules as well as the number, types, and values of capacitors.

The STILEs can also be embedded in the PCB or inside the voltage-regulator modules themselves. The startup is now supplying engineering samples of the STILE to potential customers.