P.C. Board Inductor Shrinks Buck Regulator

March 30, 2012
Buck regulators require an inductor that can be one of the largest components on the circuit board. By switching at 20MHz, the regulator can employ a special inductor consisting of copper traces on the pc board, which minimizes physical size as well as EMI.

The SC220 is a buck regulator that accepts a 2.7V to 5.5V input and produces an output as low as 1V and can drive a 650 mA load (Fig. 1). Key to its operation is a 20MHz switching frequency that allows use of small size, low value external capacitors and inductors.

The regulator’s 20MHz switching frequency permits use of inductors in the 220nH range, and enables designers to configure their own inductors directly on the pc board. This patented inductor technology, called X-EMI™, is different from conventional pc board trace inductors. Conventional board trace inductors used with high-frequency switchers exhibit significant EMI issues. X-EMI inductor technology solves EMI problems and can meet or exceed the EMI performance of conventional chip inductors (Fig. 2). This technology works by placing two small air-core inductors adjacent to each other in anti-phase position, where the magnetic fields of each air-core inductor partially cancel one another to reduce EMI. The net flux from the two inductors partially cancels the wide leakage paths caused by the wide geometry, but is still able to store the energy of the inductors in series.

These copper traces may be located on internal layers of the circuit board, so inductors should have almost no impact on the available pc board area for components on the board’s surface. Fig. 3 shows a typical pc board inductor on an SC220 demo board. Table 1 compares the characteristics of the X-EMI inductor and a chip inductor.

Table 1. Comparison of the
characteristics of the X-EMI inductor
and planar chip inductors
X-EMI Inductors Planar Chip Inductors
Magnetic field in on inductor partially cancels the other, resulting in low overall EMI. Magnetic flus flows perpendicular to the p.c. board because it is unshielded.
Low EMI without shielding Without shielding the magnetic field is parallel to the circuit board, which causes eddy current losses.
High inductance achieved by coupling. The total series inductance for two inductors is greater than the sum of the two. Higher than normal inductance cannot be achieved due to the absence of coupling.

The SC220 inductor must be capable of handling up to 1A. Typical power inductors may be too lossy at 20MHz unless specifically designed for high frequency operation. An alternative to the pc board inductor can be a wirewound RF choke, many of which are rated at 1A.


Input and output capacitors for the SC220 can also be small size and low value types. They should be multilayer ceramic capacitors, preferably with X7R or X5R dielectric. The SC220 is optimized to operate with typical 1μF input and output capacitance. In practice, the self-resonant frequency of surface mount capacitors of this type is well below the 20MHz ripple frequency, so efforts to minimize output ripple may best be focused on minimizing the inductance of the output capacitor and the length of the circuit path to ground rather than on increasing the capacitance value of the output capacitor.

The SC220 operates with a self-oscillating control method based on the output voltage ripple. This control loop compares the output voltage to an internal 1V reference to regulate the output voltage directly, adjusting the turn-on and turn-off time of the power switches so that the output voltage is held at a precise value. This configuration gives a single-cycle response to transient events. The SC220 can deliver a peak efficiency of 90%, while maintaining efficiency over 80% during light load condition. Fig. 4 shows SC220 efficiency curves using X-EMI inductor technology compared with a chip inductor.

To maintain constant frequency, a phase locked loop (PLL) synchronizes switching with an internal clock. This PLL adjusts the effective upper and lower thresholds of a comparator, thus maintaining a constant frequency. Under transient conditions, the voltage control loop determines the optimum switching pattern for maintaining the output voltage. After a short transient, the PLL brings the switching frequency back to normal. At extreme duty cycles, where the frequency control loop may not be able to maintain frequency lock even under steady-state conditions, frequency may fall, but the output voltage regulation is maintained by the main voltage control loop. Therefore, it can achieve excellent line and load transient response.

Operating Modes

The SC220 operates in two modes over a wide range of load currents. For moderate to heavy load conditions, it operates in PWM mode with a constant switching frequency. Under light-load conditions, the converter automatically enters a PSAVE mode. With the typical 220nH inductor, the transition between PWM and PSAVE mode typically occurs in the range of 100-200mA, depending on the input and output voltages. Sensing the minimum value of the ripple current controls the transition from PWM mode to PSAVE mode. When it drops below a threshold level for 32 consecutive cycles, the transition to PSAVE mode is initiated.

Under very light load conditions, the SC220 maintains high efficiency by shutting down all but the most essential circuit blocks, maintaining a typical quiescent current of about 19μA. In this mode, some circuitry used to control absolute DC accuracy is turned off. In that case, there may be tens of millivolts DC shift between normal operation and this “no-load” state. However, in the case of a load transient, the system will turn on the high-side FET within nanoseconds as a discontinuous pulse is issued. The transition to PWM mode can occur within that nominal on time, giving superior no load to full load transient response.

Once in PSAVE mode, it maintains regulation by modulating the time between fixed current pulses. When a new pulse is required by the loop before the existing pulse has terminated, the loop determines that the load cannot be maintained in PSAVE mode. This prompts an instantaneous switch from PSAVE mode back to PWM mode.

Applying a voltage higher than 1.2V on the EN pin enables the SC220, and it is disabled when the applied voltage is pulled below the logic low threshold. The EN pin can also be used to set the switching frequency: if a digital clock is fed to EN, the SC220 will sense this as a valid enable signal and the external clock will be used rather than the internal 20MHz oscillator.

An internal soft start circuit limits the inrush current during start-up with a stepped current limit. Over the course of about 40μs, the SC220 is stepped in increments of one quarter of the nominal current limit to full current limit, thereby reducing the worst-case surge current that might otherwise be reflected to the input current.

Current Limit

Fig. 5 is a simplified diagram of the SC220 showing current limit (CLIM) that protects it and the external components under overload conditions. The synchronous rectifier output stage consists of a PMOS high-side switch and an NMOS low-side switch. When the current flowing through the high-side PMOS switch exceeds the current limit, the PMOS switch turns off. The high-side switch is then held off for a period sufficient to allow inductor current to decay. When the output voltage is close to the nominal regulation point, this will look similar to constant current limiting. As the output voltage falls, the imposed off-time is such that the frequency will drop, thus the inductor will have appropriate time to reset. This may cause the average current to reduce, giving a mild ”fold-back” characteristic to the current limit, where the average load current drops as the output voltage collapses (although the peak current maintains its nominal value). In a short-circuit condition, the system runs continuously at this reduced frequency.

The SC220 features excellent regulation during line and load transients because of its proprietary control method and the high di/dt allowed by the use of a small inductor. This allows for best performance while providing the benefit of using a small low cost output capacitor. VOUT shows only tens of millivolts of ripple voltage during a load current step change from less than 1mA to 650mA within hundreds of nanoseconds, using typical a 1μF output capacitor.

Layout Considerations

The SC220 buck regulator is available in an SOIC-8 package. Proper board layout is important to achieve optimum performance from the regulator. A few fundamental layout considerations should help designers achieve the regulator’s specified performance. Poor layout can degrade the performance of the switching regulator and may contribute to EMI problems, ground bounce, and possibly poor regulation and instability.

One recommendation is to place input capacitor, CIN, as close as possible to the PVIN and PGND pins. This capacitor provides a low impedance loop for the pulsed currents present at the buck converter’s input. Use short wide traces to connect this capacitor as close to the IC as possible. This will minimize EMI and input voltage ripple by localizing any high frequency current pulses.

Furthermore, keep the SW pin traces as short as possible to minimize the pickup of high frequency switching edges to other parts of the circuit. The output capacitor COUT and the inductor should be put as close as possible to the related pins of the IC, and connected as close as possible between the SW and ground pins. And, designers should route the output voltage feedback/sense path from the output capacitor path and away from the inductor and SW node to minimize the possible noise and magnetic interference to the output feedback/sense path.

Use a ground plane referenced to the PGND pin, and the ground connection of the input and output capacitors should be put on this plane and close to each other if possible, and as close to the PGND pin as possible. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes.

Designers should also minimize the resistance from the VOUT and AGND pins to the load, which will reduce the voltage drop on the ground plane and improve the load regulation. Minimalizing the resistance will also improve the overall circuit efficiency, by reducing the copper losses on the output and ground planes.

About the Author

Sam Davis

Sam Davis was the editor-in-chief of Power Electronics Technology magazine and website that is now part of Electronic Design. He has 18 years experience in electronic engineering design and management, six years in public relations and 25 years as a trade press editor. He holds a BSEE from Case-Western Reserve University, and did graduate work at the same school and UCLA. Sam was the editor for PCIM, the predecessor to Power Electronics Technology, from 1984 to 2004. His engineering experience includes circuit and system design for Litton Systems, Bunker-Ramo, Rocketdyne, and Clevite Corporation.. Design tasks included analog circuits, display systems, power supplies, underwater ordnance systems, and test systems. He also served as a program manager for a Litton Systems Navy program.

Sam is the author of Computer Data Displays, a book published by Prentice-Hall in the U.S. and Japan in 1969. He is also a recipient of the Jesse Neal Award for trade press editorial excellence, and has one patent for naval ship construction that simplifies electronic system integration.

You can also check out his Power Electronics blog

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