Single-event burnout (SEB) is a failure mode for all power semiconductors, even at sea level. SEB is caused by cosmic radiation and can result in permanent damage to a semiconductor that is supporting voltage. Experimental SEB data date back about 20 years. Therefore, SEB is a well-documented phenomenon, yet it is still relatively unknown outside of the traction drive and aerospace design communities. An understanding of SEB can be applied to both explain and reduce random field failures in power systems that would otherwise be inexplicable.
SEB is caused by high-energy particles passing through a reverse-biased p-n junction of a semiconductor device. In an SEB event, the particle causes an avalanche trail in its wake. Whether this event causes damage depends on the energy of the particle, the semiconductor technology of the device, the type and physical design of the device, and the voltage stress around the semiconductor junction. Voltage stress is the ratio of applied voltage to breakdown voltage.
If there is no damage from particle bombardment, device parameters such as leakage current are usually not degraded. However, if the bombardment does cause damage, it is permanent and may result in catastrophic failure.
About 90% of high-energy particles at ground level are neutrons. Neutrons are from the sun and from nuclear reactions in the atmosphere with other particle types from the sun. Fig. 1 depicts a neutron bombardment of a simple p-n semiconductor junction (a diode) that is reverse-biased and, therefore, is supporting voltage. The neutron leaves an ionization or avalanche column in its wake. Carrier multiplication and the resultant heat in the avalanche column is the culprit responsible for permanent damage.
The situation with n-channel MOSFETs and IGBTs is complicated by the presence of the parasitic n-p-n transistor structure in these devices. This parasitic transistor can be turned on by particle bombardment, at least in a microscopic area, causing localized latchup and subsequent damage. Turn-on of the parasitic n-p-n transistor is apparently what makes n-channel MOSFETs and IGBTs more susceptible to SEB failure than diodes.
The reference to SEB in this article includes single-event gate rupture (SEGR), which, as the name implies, is damage to the gate of a MOSFET or IGBT that is supporting voltage. SEGR is caused by particle bombardment creating a damaging ionization column between the gate oxide and the drain. However, for this article, all radiation-induced failures are collectively referred to as SEB.
The Nature of SEB
SEB cannot be eliminated by device design. Unfortunately, there is no feasible way to design around SEB susceptibility. The failure rates of one manufacturer are typical of any competing manufacturer for the same basic semiconductor technology.
A common myth is that SEB is due to component quality issues or assembly defects or, alternatively, to a bad design or a poor layout. Rather, the true cause is cosmic radiation. As such, it cannot be fully understood using Arrhenius reliability models (though SEB may explain useful-life-period failures).
SEB is not related to excessive avalanche energy. SEB can occur even when a device is not in an avalanching state (in which the applied voltage exceeds the device breakdown voltage).
Of vital importance is the fact that SEB can cause field failures that are otherwise inexplicable, and the failure rate can be quite high.
Factors Affecting SEB
Fig. 2 shows a partial list of parameters and their relative impact on the SEB failure rate. Semiconductor technology has a huge effect. For example, the wide bandgap of silicon carbide makes it much more radiation hardened than conventional silicon. Diodes are also less susceptible to SEB than MOSFETs and IGBTs, but they are still susceptible. P-channel MOSFETs are practically immune to SEB failures. In any case, choosing among these semiconductor technologies is usually not an option available to circuit designers.
Like semiconductor technology, the applied voltage stress has a significant effect on the SEB failure rate. Increasing the applied voltage greatly increases the probability of SEB failures. Conversely, decreasing the applied voltage greatly increases reliability, as will be shown.
Semiconductor junction area is determined by output power, cooling and operating condition requirements. It is not feasible to significantly reduce the SEB failure rate by decreasing the size or number of devices in the circuit. In general, the higher the circuit's output power, the greater its susceptibility to SEB failures. Fig. 2 clearly shows that applied voltage stress is the only practical factor a circuit designer can adjust to limit the SEB failure rate. The system voltage levels, the voltage ratings of semiconductor devices or both can be selected to yield an acceptable SEB failure rate.
Several experimental results have been published, both time accelerated by a particle accelerator, and nonaccelerated.[1-3] Rather than delving into each experiment and a discussion of theories and device physics, only extrapolations of some experimental results are presented here. These results match well with reported field failure rates.
However, it is important to note that, because of the number of uncontrolled variables involved with SEB, it is only feasible to get a general idea of what the field failure rate might be. Accuracy to within an order of magnitude is considered to be quite good. Still, extrapolation from experimental data matches well with actual field failure cases where the failure rate was greatly reduced by reducing the voltage stress, verifying that most failures were indeed caused by SEB.
Fig. 3 shows the SEB failure rate in FITs — defined as one failure in one billion hours — for a single MOSFET in a TO-247 package that is continuously supporting voltage (turned off). Note that a failure rate of 1 FIT is equivalent to a mean time between failures (MTBF) of one billion hours, or an annual failure rate of 0.000876%.
The data for Fig. 3 were gathered at sea level and room temperature. MOSFETs from various manufacturers and with various voltage ratings were set up to applied voltage. Failure rates at a number of different applied voltage stresses were recorded. Using the breakdown voltage temperature coefficient, the data were adjusted from room temperature to 100°C. Finally, curves were fit to the adjusted data. Three curves are shown: one for 500-V or 600-V MOSFETs or IGBTs, another for 800-V to 1200-V MOSFETs or IGBTs and a third for 1700-V IGBTs. The 1700-V curve was actually extrapolated from the other two curves. Similar experiments to those described in reference 1 were performed by Microsemi, and the results match well with the previous data.
A few important concepts can be learned from the data in Fig. 3. First, even in terrestrial applications, the SEB failure rate can be surprisingly high. Second, a 5% reduction in voltage stress results in a reduction in the failure rate by a factor ranging from 5 to 10. Again, reducing voltage stress is by far the most powerful method of reducing the SEB failure rate. Third, the higher the operating voltage is, the higher the susceptibility to SEB is. Higher-voltage-rated devices need more voltage derating (less voltage stress) than lower-voltage devices. Voltage derating data for higher-voltage-rated devices are available in datasheets or other technical literature. Fourth, the failure rate drops off with lower-voltage stress, which is consistent with experimental data.
The SEB failure rate drops with increasing temperature because the breakdown voltage rises with increasing temperature, reducing voltage stress. Using 100°C is conservative if your operating temperature is actually higher. If your operating temperature is lower, you can adjust the voltage stress by about -0.05%/°C. The failure rate scales directly with silicon area and duty factor. (Devices fail due to SEB only when turned off; the turn-off state is indicated by the duty factor, which equals 100% minus the duty cycle.)
Applying SEB Data
While it is not possible to determine the SEB failure rate exactly, simple guidelines can at least assure that the SEB failure rate is well within your design reliability targets. The table shows the recommended maximum voltage stress for various numbers of TO-247 devices in the circuit, covering both a 50% duty factor and a worst-case duty factor of 0%. The operating junction temperature in the table is 100°C, and the voltage waveform is assumed to be rectangular. Voltage stress for other duty factors can be determined by simple extrapolation. The conversion factors between the TO-247 package and other popular packages and modules are shown in Fig. 4.
The failure rates of 10 FITs and 100 FITs are shown in the table, corresponding to approximately 0.01% and 0.1% system failures per year, respectively. These are very low failure rates. Voltage stress for higher-allowable failure rates can be extrapolated directly from the table.
These SEB data can be applied in the design phase to improve overall reliability by reducing the risk of SEB failures. One example would be the design of a high-power phase-shifted bridge using 500-V MOSFETs in the SP3 module package. The bus voltage is 385 V, resulting in a voltage stress of 77%.
Fig. 4 shows that an SP3 module package can contain up to 12 times the silicon area as a single TO-247 package. There is no row for 12 devices in the table, but by interpolating between 8 and 16 devices, you will find that the maximum recommended voltage stress is 74% and 79% for failure rates of 10 and 100 FITs, respectively (the duty factor is 50% in a phase-shifted bridge). Based on this, it should be safe to operate with a 400-V bus voltage if the reliability goal for SEB failures is 100 FITs.
As another example, the same SP3 module package could be used in a phase-shifted bridge, but with the bus voltage set to 800 V and using MOSFETs rated for 1000 V. The table indicates that the recommended maximum voltage stress is 65% and 70% for 10 and 100 FITs, respectively. The voltage stress is 80%, which is significantly higher than recommended.
Fig. 3 shows that for a single TO-247 with a 0% duty factor (which represents a worst-case condition for the devices that are constantly turned off), the failure rate would be about 700 FITs. This figure is multiplied by 12 to scale from a single TO-247 to the SP3 module, and then multiplied by 0.5 to take into account the 50% duty factor. The result is 4200 FITs, or 3.7% per year, which is rather high.
Note that this SEB failure rate does not include failures from other portions of the system, such as PFC or output stages. It also doesn't account for other failure types such as circuit-design flaws, shipping damage and wear-out mechanisms, among other problems. These potential failures also must be considered to meet the overall reliability goal.
The risk of SEB failures will never be zero. The designer must choose an acceptable failure rate, knowing that SEB will cause some devices to fail. Measures used to reduce SEB failures can negatively impact system efficiency, performance specifications and cost. This highlights the general difficulty of achieving high reliability at low cost in any electronics system.
If, for example, the SEB failure-rate budget for the phase-shifted bridge is 10 FITs, then there would be three potential options. The first option would be to choose a higher voltage rating for the module. The second option would be to reduce the bus voltage in the system. And the third, a combination of the first two options, would be to both use a higher voltage rating and reduce the bus voltage.
If 1200-V MOSFETs were to be used, this decision would result in a significantly higher conduction loss due to the difference in on-resistance values between 1000-V and 1200-V MOSFETs. To compensate for this performance penalty, it may be necessary to use a larger module or even to switch to IGBTs. However, with a full understanding of SEB risks, it may be possible to achieve the same reliability goal at much lower cost through system-level tradeoffs. Uncovering all the options for reducing SEB failures will require additional effort, but the availability of these options has obvious benefits for optimizing a design before the product goes into production.
If 1200-V MOSFETs are used and the bus voltage is kept at 800 V, the voltage stress drops to 67%. From the table, the maximum recommended voltage stress is 65% for 10 FITs. Because of the inherent uncertainty in predicting SEB failure rates, this option might be marginal.
In borderline cases such as this, it is important to remember the nonexact nature of estimating SEB failures. First, the data are approximate extrapolations from data taken under a certain set of conditions. It is unknown how closely the approximate data would match a particular system installation. For example, a system might be installed in a basement where there is some neutron shielding. Two meters of concrete will reduce the neutron-flux density by a factor of 10. Other factors in borderline cases come into play such as elevation (altitude) and latitude.
To be sure of meeting a certain failure-rate goal, it is necessary to operate below the maximum recommended voltage stress listed in the table. In addition to using 1200-V rated devices, reducing the bus voltage from 800 V to 750 V would result in 63% stress and a reduction in the SEB failure rate by a factor of 5 to 10 (by inspection of Fig. 3). This should certainly meet the SEB failure-rate budget of 10 FITs.
Diodes have a lower susceptibility to SEB than MOSFETs and IGBTs. Therefore, applying the previous MOSFET/IGBT design guidelines to diodes ensures an even lower probability for diode SEB failures.
Nonrectangular Voltage Waveforms
Some resonant circuits do not have rectangular voltage waveforms. Since the SEB failure rate is highly nonlinear with voltage stress, simply taking the average off-state voltage applied to a particular device results in a voltage stress that is too low.
For example, when using four TO-247, 1000-V MOSFETs in a resonant circuit, the off-state voltage rings up to an 800-V peak. The resulting sinusoidal waveform would have a switching duty factor of 50%. If the voltage stress is taken as the average, then the stress during the sinusoidal ringing is only 0.707 × 800 peak voltage, or 566 VPK. With 1000-V rated MOSFETs, this translates to only 57% voltage stress, which is deceivingly lower than the maximum recommended stress of 73% from the table for an SEB goal of 100 FITs or less.
For a more accurate prediction of reliability, the sinusoidal ringing can be divided into three portions: two are when the drain-source voltage is less than 566 V and the third is at or above 566 V, as shown in Fig. 5. For convenience, the entire higher-voltage segment is taken as the peak value, which is 800 V in this case. This practice is both simple and conservative.
Looking at Fig. 3, 80% voltage stress results in an SEB failure rate of about 700 FITs for a single TO-247, 1000-V device, which translates to 2800 FITs for the four devices in our resonant circuit, but this only applies to a portion of the waveform. The highest voltage segment persists for half the off-state period, and the off-state period is half the switching period. Therefore, the highest drain-source voltage segment occupies 25% of the switching period. Because the SEB failure rate scales with the duty factor, the SEB failure rate due to the high-voltage segment is approximately 2800 FITs × 25%, or 700 FITs. Even though this is a conservative estimate, it is still significantly higher than the design goal of 100 FITs.
Using 1200-V MOSFETs or IGBTs, we would have 67% voltage stress during the highest-voltage off-state time. From Fig. 3, a single TO-247 device would have a FIT rate of about 3 (continuously off). Our system would have a failure rate of about four TO-247 devices, multiplied by 3 FITs per TO-247 device and then multiplied by 25% (for the duty factor). This would result in 3 FITs, and this figure represents extremely high reliability against SEB failures. Clearly, the information obtained from the more detailed analysis of nonlinear voltage waveforms can produce designs that are more reliable.
Unfortunately, it is almost impossible to distinguish SEB failures from many other failure types. SEB failures are typically a burn spot in the active area (Fig. 6), but this failure “signature” also could be caused by excessive reverse-recovery dV/dt of the body diode, or a short-circuit event. Usually the die is burned so badly there is no way to determine the exact cause.
With no unique failure pattern, it is almost impossible to conclude that SEB was the cause of any particular failure. Therefore, laboratory failure analysis of a specific device failure will not be sufficient for this purpose. Rather, the determination of whether SEB failures are actually happening (as well as whether or not they are likely to happen) must be made through statistical analysis. This analysis must be based on published data about recorded SEB-related device failures. It also requires an understanding of the SEB failure mechanism itself. PETech
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Normand, E.; Wert, J.; Oberg, D.; and Majewski, P., “Neutron-Induced Single Event Burnout in High Voltage Electronics,” IEEE Transactions on Nuclear Science, December 1997.
Davidson, C., Blackmore, E. and Hess, J., “Failures of Terrestrial MOSFETs Due to Single Event Burnout,” International Telecommunications Energy Conference, September 2004, pp. 503-507.