As shown in Fig. 1, Fairchild Semiconductor's PowerTrench MOSFETs have exhibited significant improvements from one generation to the next. The company's original PowerTrench, which presented improvements over previous planar MOSFETs, is shown in Fig. 1a, while in Fig. 1b, the oxide underneath the gate region was extended, resulting in improved QGD (reduced switching loss). Fairchild's newest generation is a shielded-gate power MOSFET (Fig. 1c).
The new shielded gate device is said to offer performance improvements such as:
- Lower COSS (output capacitance)
- Lower QRR (reverse recovery charge)
- Lower tRR (reverse recovery time)
- Enhanced low-side efficiency performance due to the lower COSS and tRR
- Low RDS(ON)
- Low QG (total gate charge)
- Very low QGD
THE SHIELDED GATE
The equivalent circuit of Fig. 2 demonstrates the impact of the shielded gate. Two capacitances, CDrain-Shield and CGate-Shield — inserted with dashed lines in the equivalent circuit — act as virtual snubbers to minimize ringing when the MOSFET switches.
Fig. 3 compares the switching characteristics of a new shielded-gate PowerTrench MOSFET (Fig. 3a) with one of the competitor's lateral processes (Fig. 3b). The shielded-gate device exhibits considerably less ringing than the competitor MOSFET.
THE IMPORTANCE OF PACKAGING
Also helping switching performance is the use of a molded lead package (MLP) to minimize parasitic capacitance and inductance from the silicon die to the output terminals. The small die also allows for a dual-MOSFET package that simplifies the design of synchronous rectifiers. Fig. 4 shows a typical version of dual PowerTrench MOSFETs configured as synchronous rectifiers. The package contains two dice. The bottom device is a PowerTrench SyncFET™ with an integrated Schottky diode, and the top device is a conventional PowerTrench MOSFET with its standard body diode.