The Evolution of Power MOSFETs and the Role of Process Technologies

As shown in Fig. 1, Fairchild Semiconductor's PowerTrench MOSFETs have exhibited significant improvements from one generation to the next. The company's original PowerTrench, which presented improvements over previous planar MOSFETs, is shown in Fig. 1a, while in Fig. 1b, the oxide underneath the gate region was extended, resulting in improved Q_GD (reduced switching loss). Fairchild's newest generation is a shielded-gate power MOSFET (Fig. 1c).

The new shielded gate device is said to offer performance improvements such as:

• Lower C_OSS (output capacitance)
• Lower Q_RR (reverse recovery charge)
• Lower t_RR (reverse recovery time)
• Enhanced low-side efficiency performance due to the lower C_OSS and t_RR
• Low R_DS(ON)
• Low Q_G (total gate charge)
• Very low Q_GD

THE SHIELDED GATE

The equivalent circuit of Fig. 2 demonstrates the impact of the shielded gate. Two capacitances, C_Drain-Shield and C_Gate-Shield — inserted with dashed lines in the equivalent circuit — act as virtual snubbers to minimize ringing when the MOSFET switches.

Fig. 3 compares the switching characteristics of a new shielded-gate PowerTrench MOSFET (Fig. 3a) with one of the competitor's lateral processes (Fig. 3b). The shielded-gate device exhibits considerably less ringing than the competitor MOSFET.

THE IMPORTANCE OF PACKAGING

Also helping switching performance is the use of a molded lead package (MLP) to minimize parasitic capacitance and inductance from the silicon die to the output terminals. The small die also allows for a dual-MOSFET package that simplifies the design of synchronous rectifiers. Fig. 4 shows a typical version of dual PowerTrench MOSFETs configured as synchronous rectifiers. The package contains two dice. The bottom device is a PowerTrench SyncFET™ with an integrated Schottky diode, and the top device is a conventional PowerTrench MOSFET with its standard body diode.

MOSFET FAMILY COMPARISONS
PART NO. PACKAGE V_DS (V) 25°C I_D CONT.(A) 25°C POWER (W) TYPICAL V_GS(TH) (V) TYPICAL R_DS(ON) 10V I_D/(mΩ) 10 V Q_G (N^C) FIGURE OF MERIT R_θJC °C/W TYP. C_OSS V_GS=0 F = 1 MHz V_DS/(PF) Old FDMC8854 Power 33 30 15 2.0 1.9 15 A/4.4 41 180 3.0 10 V/515 SG FDMC7570S 3 × 3 MLP 25 27 2.3 1.7 27 A/1.6 49 79 2.1 10 V/1,010 Old FDMS3672 Power 56 100 22 2.5 3.1 7.4 A/19 31 589 1.6 50 V/210 SG FDMS86101 Power 56 100 49 2.5 2.9 13 A/6.3 39 246 1.2 50 V/460 *SG = shielded gate