Multiple Metrics Define Performance in Super-Junction MOSFET Selection

Nov. 1, 2010
Application differentiation and market needs will likely see a wide range of power MOSFET offerings in varied cost and performance available, addressing different system needs and customer budgets.

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The decade-long evolution of super-junction MOSFETs has seen the silicon limit broken, the ongoing reduction of area specific RDS[ON] and continued chip size reduction leading to attendant cost/performance improvements [1]. Yet, these improvements have not solved all the power designer's problems!

In fact, success in attacking some performance issues around gate charge have led to new challenges in completing a robust design, particularly if good layout practices are not understood [2]. This is where understanding the underlying application issues and how they relate to the MOSFET electrical characteristics becomes quite important, because we can dig deeper into optimizing high voltage MOSFET behavior through knowledge of specific application issues. Then, patterns begin to emerge about the performance and characteristic changes needed for different topologies and classes of operation. Keeping that concept in mind, we will explore the continuing evolution of super-junction MOSFETs in the industry, as pioneered by CoolMOS 10 years ago, and looks at the directions for continued development.

First, area-specific RDS[ON] has improved significantly compared to the technology highlighted 10 years ago in PCIM. In 2005, production CoolMOS technologies improved area specific RDS[ON] by about 35%, reducing the on-state resistance from 39 mΩ/cm2 to about 25 mΩ/cm2 [3,4]. This technology step also included substantial reductions in QGD switching charge of the MOSFET- overall as much as 60-65%. Fig. 1 compares gate charge characteristics of three 190-199 mΩ FET families — C3 (2003), CP (2005) and C6 (2009) — switched at 20A load current. Coupled with significant reductions in COSS output capacitance, which is a primary loss mechanism in hard switching, switching efficiency of the CP generation was substantially improved over that of C3 [3, 4, 5]. All of this is very well and good, but is this the answer to everyone's performance prayers? If we delve more deeply into other application requirements, we may see that's not the case.


While there are many application topologies and possible operating modes, we will focus on just a few popular ones very commonly used. A major category long in service is the single-ended hard switching topology, whether direct or indirect mode (forward or flyback or boost), either in DCM (discontinuous conduction mode), CrCM (Critical Conduction mode), or CCM (Continuous Conduction Mode). The first two run triangular current waveforms with zero initial current and low turn-on loss; the performance requirement is for minimum conduction resistance and low turn-off loss at high current. Here, the SJ concept MOSFET works well, because of the area specific RDS[ON] and the non-linear capacitive snubber effect of the output capacitance [3, 4]. Low COSS also leads to low EOSS at turn-on, aiding DCM performance. In these topologies, the quasi-ZVS mode turn-off lends efficiency advantages, with the conduction channel turning off quickly and the output capacitance merely being charged by inductive load current at turn off.

The low gate charge of CoolMOS CP is a function of low gate-drain overlap capacitance, which improves switching speed but lowers “control” of di/dt. In most of these topologies, especially when transformer coupled, this doesn't usually pose a problem, as intrinsic circuit impedances tend to limit di/dt and dV/dt. With circuits like the PFC boost converter, the low circuit impedances and potential for high di/dt and dV/dt requires more care by the designer. The flip side of low gate charge is low CRSS, and more sensitivity to PCB layout. Fig. 2 illustrates the nature of the configuration of MOSFET and PCB parasitics, which if not in the right proportions can lead to oscillatory behavior at turn-on and turn-off. Besides the internal drain-to-gate feedback capacitance, there is an external capacitance largely determined by the MOSFET package and the PCB foil layout. Worse yet, the external capacitive influence is coupled through parasitic inductances, leading to some additional phase shift. Minimizing the external drain to gate coupling capacitance is the key, coupled on occasion with palliative measures such as ferrite beads with substantial resistive loss at 100 MHz, on the order of 30-50 Ω [1]. Then clean fast switching is obtained; in fact, very fast switching. For some topologies and applications, it will be too fast.

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So, while this class of application is well served by the very fast switching and low turn-off loss of CP, in other applications, a literally more measured approach is necessary. This was a significant component of the development thrust for the C6/E6 series introduced in 2009, where controlled di/dt and dV/dt were mandated over a wide load current range. Why was that needed?

Looking at applications like totem pole inverter stages with or without reactive current flow through the body diode, a focus on controlled switching speed is a necessary approach, even when the MOSFETs are quite rugged at high speeds. This is driven by the limitations of the majority of floating drivers or half-bridge configured driver products, which often have CMRR (Common Mode Rejection Ratio) upper limits in the range of 15-40V/ns. While reducing output capacitance lowers turn-on losses, it also leads to higher dV/dt. Reasonably fast voltage/current crossover speed for controlled losses needs to be combined with controlled di/dt and dV/dt over a wide load current range, so that as load current increases, a controlled switching rate is maintained. This requires care in engineering the gate overlap capacitance and providing gate control of switching rates over a wide drain current range up to typical maximum link voltages, usually in the range of 400V.

For applications requiring body diode conduction and hard commutation recovery of the body diode, the application has even stricter requirements. A carefully engineered approach to the intrinsic body diode as well as the gate capacitance overlap is required to enable consistent robust performance in these high power bridge type applications, as well to control di/dt and peak overshoot voltage during commutation recovery. This dictates the inclusion of an optimized lifetime killing process to reduce body diode Qrr [6]. This is even more critical for the super-junction MOSFET with its compensation structure columns, because typical behavior of the compensation columns is to limit the diode voltage rise until essentially all carriers have been swept out of the lower epitaxy near the substrate. This typically results in an abrupt collapse in current and high di/dt at the end of the commutation interval. The high collapsing di/dt then causes dv/dt through the inverter loop inductance, with the potential to develop over-voltage spikes and avalanche. Fig. 3 highlights improvements possible in total Qrr and recovery end slope possible with improved design and processes.


These application concerns highlight that there is more to HV MOSFETs than just area specific RDS(ON). Yet, the race is clearly on for improvements in that metric, as a sampling of the available published papers shows in Fig. 4. These publications are just the tip of the iceberg of the developments underway at industry leaders.

The challenge for improving area specific RDS[on] of super-junction MOSFETs lies not in the conceptualization of the necessary structures, but in the development of feasible manufacturing processes- achievable in commercial quantities and yields, with high process Cpk. At the heart of this difficulty is the fundamental physical relationships required for low area specific RDS[ON]: the column aspect ratio, which limits the doping that may be used for a given blocking voltage target.

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Super-junction column aspect ratio ASJ = tSJ/WSJ, where tSJ is the height of the charge compensation columns (p columns under the main p-wells), and WSJ is the cell pitch. Then for a SJ MOSFET: RDS[ON].Aα1/ASJ. The implication of these relationships is the necessity to fabricate high aspect ratio columns with consistency and the required charge balance, with relatively high doping profiles. Fig. 4 documents some of the area-specific RDS[ON] results of published research efforts, mainly using a trench filling approach borrowed from DRAM fabrication, instead of the multi-epi growth with annealing used for most existing generations of commercial products. Recent papers [7] even focus on newly developed measurement and analysis techniques needed to evaluate structures and process development, in order to develop the control needed for commercial processes. Other process approaches such as high-energy implant have demonstrated laboratory feasibility, but have drawbacks for use as a production process [8].

While Izak Bencuya expected significant advances in production devices as long ago as 2005 [9], these have been slow to materialize in commercial volume, probably due to the difficulties in implementing trench filling processes with commercial yields. Still, the historical trends of development as outlined by Bencuya would indicate we're overdue for some significant advance in commercial devices. But the difficulties of fabrication and likely process complexity may position these components as an intermediate solution for only high performance applications where some extra cost is acceptable, not the likely much higher pricing anticipated to be seen for SiC and GaN solutions predicted for the 2011 to 2012 time frame. Application differentiation and market needs will likely see a wide range of product offerings in varied cost and performance available, addressing different system needs and customer budgets.


  1. J. Hancock, F. Bjork, G. Deboy, “AN-CoolMOS-CP-01 Application Note CoolMOS CP”, published by Infineon Technologies, AG, Austria.

  2. L. Lorenz, I. Zverev, J. Hancock, “Second Generation CoolMOS Improves on Previous Generation's Characteristics”, PCIM Magazine, Nov. 2000.

  3. J. Hancock, “Meeting the Challenge for OfflineSMPS Through Improved Semiconductor Current Density”

  4. J. Hancock, “Superjunction FETs BooST Efficiency in PWMs”, Power Electronics Technology Magazine, July 2005.

  5. J. Hancock, “Bridgeless PFC Boosts Low-line Efficiency”, Power Electronics Technology Magazine, February 2008.

  6. G. Deboy, J. Hancock, M. Puerschel, U. Wahl, A. Willmeroth, “Compensation devices solve failure mode of the Phase Shift ZZVS Bridge during light load operation”, Proceedings APEC Conference 2002.

  7. S. Ono, L. Zhang, H. Ohta, M. Watanabe, W. Saito, S. Sato, H. Sugaya, and M. Yamaguchi, “Development of 600V-class trench filling SJ-MOSFET with SSRM analysis technology”, ISPSD 2009.

  8. M. Rub, M. Bar, G. Deboy, F.J. Niedernostheide, M. Schmitt, H. Schulze, Al. Willmeroth, “550V Superjunction 3.9 Ω/mm2 Transistor Formed by 25 MeV Masked BoRDS[on] Implantation”, ISPSD 2004.

  9. I. Bencuya, “The Future of Power Semiconductors”, APEC 2005 Plenary.

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