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First generation CoolMOS™ technology, developed for the production of charge compensated devices, employed a novel internal structure that offered low on-resistance with a completely altered voltage dependence of device capacitances. The new second generation CoolMOS improves ruggedness aspects such as avalanche and short circuit behavior and reach the limit of active zener clamped devices. The second generation's improvements allow these devices to cover a broader range of applications.
To understand the advantages of CoolMOS or any other power semiconductor it is important to look at power electronic system engineering, particularly in terms of energy saving, control dynamics, noise reduction and volume and weight minimization. The impending technology shift in power electronics is being driven by the following requirements:
- Energy saving through use of new circuit topologies based on ultra low loss power semiconductors
- Intelligent energy management
- Miniaturization of electrical systems through the use of ultra fast switching components.
- Cost reduction through system integration
The prime movers driving the technology shift in power electronics are the pressure to rationalize the use of energy, cost optimization of power electronic system solutions and intelligent power management.
Increasing power densities, cost pressure and an associated greater utilization of the robustness of modern power semiconductors are making thermal system optimization more and more important in conjunction with the electrical optimization. Simulation models offering a combination of these domains have not been available previously.
CoolMOS CONCEPT
On-resistance of the conventional high voltage power MOSFET is dominated by the resistance of its voltage-sustaining drift zone. The blocking capability of this region is determined by its thickness and the doping. To increase the blocking voltage, the doping must be simultaneously reduced and the layer thickness increased. The resistance of the transistor therefore increases disproportionately as a function of its blocking capability. Accordingly, the drift zone causes over 95% of the total on-resistance in a 600V transistor. The main emphasis in improving the transistor's performance must therefore be directed toward reducing this drift region resistance.
The CoolMOS concept (Fig. 1 ) offers a new approach to overcome the drift-zone resistance challenge. The electrical conductivity is provided only by majority carriers. There is no bipolar current contribution, and hence the switching losses are equal to those of conventional MOSFETs. The doping of the voltage-sustaining layer is raised by roughly one order of magnitude by inserting additional vertical p-stripes into the structure, which compensate the surplus current-conducting n-charge. When the transistor is reverse-biased, a lateral electric field is built up, which drives the charge toward the contact regions. The space charge layer builds up along the physical p-n junction line and spreads at a voltage of around 50V across the whole p-n-striped structure. The drift zone is now completely depleted and acts like the voltage-sustaining layer of a p-n structure. If the voltage is further increased, the electrical field rises linearly without any further expansion of the space charge layer. The current flows through the space charge layer. Both carrier types are driven toward the contacts by very low electric fields within their columns. This behavior is characteristic for charge compensated devices and leads to extremely low losses. This gives an almost linear relationship between the specific resistance and the maximum blocking capability of the transistor shown in Fig. 2 .
The switching behavior of these transistors corresponds to that of conventional MOSFETs. However, the gate charge, and with it the necessary activation power of the transistor, is reduced due to the possible reduction in chip area, as compared with a conventional MOSFET with the same on-state resistance. This technology allows an on-resistance of 190mΩ at 600V and 270mΩ at 800V for a TO-220 device.
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DYNAMIC BEHAVIOR
The nonlinear spread of the space charge layer as a function of voltage can easily be observed in the characteristic output capacitance. This is reflected in the resulting drain — source capacitance, Cds, curve (Fig. 3 ). Due to the drastically increased internal surface of the p-n junction, this capacitance shows large values at low blocking voltages. However, an increase in the blocking voltage causes the internal p-n-striped structure to deplete. Both, the reduction of this surface and the expansion of the space charge layer width lead to a nonlinear behavior of the output capacitance, resulting in a lower value than a conventional MOSFET at the same Vds, and hence lower switching losses. The gate-drain capacitance shows a similar internal mechanism. The gate-source capacitance benefits from the shrink potential of the new concept compared with conventional MOSFETs.
Due to smaller chip areas, CoolMOS transistors exhibit very low gate charge values compared with RDS(on)-identical transistors implemented in conventional technology. Driver
power, Pg, is:
Pg= Qg×Vgs×fsw (1)
Where:
Qg= Gate charge
Vgs= Gate-source voltage
fsw= Switching frequency
Rise and fall times of the drain-source voltage during the switching process — and therefore the switching losses — are determined by the charging process of the gate drain feedback capacitance (Miller capacitance, Cgd). The lower the Qgd in particular, the lower the switching losses. The drastic reduction in the gate charge in the new CoolMOS technology is very beneficial when driving the device. As a result, a CoolMOS transistor can be operated with the lowest control power, the cheapest driver circuit and the highest switching frequencies.
From an application viewpoint, the high value of Cds at low voltages acts like a turn-off-relief network (“built-in snubber”). Energy stored in the device's output capacitance is:
It is very important at high switching frequency, high-voltage applications (VDS(max) > 200V) that Eds is lower than in the case of RDS(on)-identical transistors of standard MOSFET technology (Fig. 3 ). This energy, which is converted into heat during every turn-on process, increases with the chip area and therefore limits the minimum attainable power loss in hard switching circuit topologies. Due to the optimized parameters of RDS(on) and Eds and their low input capacitances, CoolMOS transistors are superior to conventional power MOSFETs at both low and high switching frequencies.
NEW CoolMOS
Second generation CoolMOS, called the C2 type, reduces switching time. Together with the low gate charge of CoolMOS devices and the drastic reduction of internal gate resistor, switching time is almost unlimited but in all parameters adjustable like in a conventional power MOSFET. This new generation of CoolMOS has a completely different gate structure than the first generation (S5 type). The new gate structure provides an internal gate resistance of less than 1Ω and is almost independent of chip size. The main question in many applications is how to adjust the switching times, di/dt and dv/dt. To answer these questions the following investigations have been done. The controllability of the di/dt- and dv/dt values of CoolMOS is a major requirement for the application engineer.
Noise emission and oscillation (ringing) is proportional to the di/dt- and dv/dt-slopes during the turn-on and turn-off transients. Further investigations have been done in a test setup by varying only the external gate resistor values and using a 600V SiC (a prototype SDP06S60) as a commutated diode.
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Figs. 4 and Fig. 5 demonstrate the drain current and source voltage slopes, respectively, during the turn-off transient for various values of external gate resistor. The turn-on behavior is controllable in the same manner.
In many applications the free-wheeling diode is of great importance. To optimize a diode the criteria like forward voltage drop, reverse recovery change and soft behavior must be considered. Fig. 6 shows the behavior of a conventional diode compared with a CoolMOS diode, a fast epi diode and a SiC diode.
AVALANCHE RUGGEDNESS
Avalanche-proof transistors reduce the reverse voltage safety margin required to handle overvoltages, which means that in many applications comparatively low-blocking transistors can be used which are smaller in terms of chip surface area and therefore less expensive for the same RDS(on). With the conventional high voltage MOSFET this was extremely important, because RDS(on)was disproportionately dependent on the breakdown voltage. For example, with conventional technology the resistance of an 800V transistor is a factor of two higher than that of a 600V transistor of the same surface area, whereas in the new CoolMOS technology this relationship means that it is only approximately 50% higher. This is a major advantage when using higher-blocking power MOSFETs. The question must therefore be precisely examined as to whether a high-blocking MOSFET that is not operated in avalanche mode does not have advantages in respect of the overall power dissipation budget. Note that the power dissipation can be very quickly assume high values due to the energy additionally converted in the transistor in avalanche mode at high switching frequencies. These new high-voltage MOSFETs also incorporate knowledge derived from avalanche-proof S-FET technology, so that a high degree of avalanche protection can also be guaranteed for the CoolMOS transistors.
Like conventional MOSFETs, CoolMOS transistors are avalanche rugged. Due to their unusual drift region design, which allows a 5X reduction in on-state resistance per chip for 600V transistors, some characteristics are modified in comparison with conventional MOSFETs. Fig. 7 shows typical avalanche voltage as a function of temperature and current density for 600V CoolMOS transistors. There is a more pronounced temperature coefficient of avalanche voltage and the dynamic output impedance is higher, resulting in higher avalanche voltage with increasing current. This can be advantageous because it allows a faster reset of avalanche inductance in many applications. Fig. 8 shows the “worst case device” characteristic curve for V(BR)dss as a function of junction temperature. At 100°C the minimum avalanche voltage is over 640V, and at 150°C it is over 670V.
CoolMOS transistors include a combination of technologies to provide high levels of avalanche mode ruggedness. The capability of CoolMOS transistors is additionally enhanced by the thin chip manufacturing technology developed for IGBTs, making it possible to produce CoolMOS chips that are only 175µm thick, less than one-third the thickness of conventional power MOSFET transistors. This reduction in thickness substantially improves the thermal impedance between the heat generating epitaxial layer and the package.
Table 1 compares conventional avalanche rugged TO-247 MOSFET transistors with industry standard part numbers and the SPW20N60C2 CoolMOS transistor with similar current ratings in the same package type, but uses only slightly more than one-half the silicon chip area. This comparison highlights that the SPW20N60 offers current capability comparable to the 500V transistor, with lower total power dissipation due to lower RDS(on). The SPW20N60 also offers the voltage headroom of the 600V transistor under overvoltage conditions, and the same peak avalanche current as the 500V device and nearly 20% higher that the 600V competitive transistor.
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THERMAL ISSUES
Increasing power densities, cost pressure and an associated greater utilization of the robust properties of modern power semiconductors are making thermal system optimization more important in relation to electrical optimization. New simulation models offer a combination of these two different domains which have been kept separate up till now.
Circuit simulators have become standard tools in the development and optimization of electronic systems. However, simulation has so far been limited to the electronic functions because the simulation models currently available allow the temperature dependence to be taken into account at best by changing the static global temperature.
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A maximum junction temperature is specified for all semiconductor components. If it is exceeded, destruction or permanent damage can occur even during transient events, such as avalanche or short-circuit operation. The maximum permissible junction temperature must not be exceeded — a problem that is almost impossible to solve by conventional means, i.e. using the Zth diagram.
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Within the safe operating range the lifetime of semiconductor components is affected decisively by temperature fluctuations. Every change in temperature causes mechanical stress in the component that affects the solder and bond connections. It is not the absolute temperature that is critical, instead it's the temperature deviation.
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The on-resistance of a MOSFET and thus the conduction losses are roughly doubled as temperature is increased from 25°C to 150°C.
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The threshold voltage of a MOSFET drops with increasing temperature, thus reducing the noise margin at the control node.
In view of these aspects, the question of the chip or junction temperature is also becoming increasingly important for circuit design. Some of the over-dimensioning in the switching of lamps or motors to cover temporary overloads is no longer necessary when the brief excess power loss can be compensated by suitable coupled heat capacitances.
The same applies when conventional protection circuits are dispensed, thanks to the high robustness of modern semiconductors. Many modern power MOSFETs are now specified with respect to avalanche. For example, a pulse pattern below the rated current is permissible as long as it can be ensured that the junction temperature at the peak does not exceed the maximum value. To simulate the time-dependent temperature curves occurring in all operating states, it is necessary to couple the electrical model of a component dynamically with the description of its thermal properties.
SIMULATION MODELS
PSpice simulation models have been developed for all CoolMOS™ devices. The models are available via Internet at www.infineon.com./products/power/simulat.htm.
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There are two levels of complexity. The basic level-1 models consider the global temperature as the static device temperature. The temperature dependence of these characteristics are implemented: output and transfer characteristics, threshold voltage, on-state resistance,• inverse diode series resistance, and drain-source breakdown voltage.
A newly developed description of the voltage dependent CoolMOS™ capacitances provides very good results in modeling the switching behavior. In addition to this, level-3 models developed for CoolMOS provide an interactive coupling of the thermal device description with the electrical MOSFET model. as shown schematically in Fig. 9 .
REFERENCES
Coe, US-Patent 4,754,310, (1988)
Chen,US-Patent 5,216,275, (1993)
Tihany, US-Patent 5,438,215, (1995)
G. Deboy, M. März, J.-P. Stengl, H. Strack, J. Tihany and H. Weber,“ A new generation of high voltage MOSFETs breaks the limit line of silicon”, pp. 683-685, Proc. IEDM (1998)
L. Lorenz, G. Deboy, M. März, J. P. Stengl, A. Bachofner, “Drastic Reduction of ON-Resistance with CoolMOS™”, pp. 250-258, PCIM Europe, 5 (1998)
G.Deboy, L. Lorenz, M. März, “Kühle Lösungen für heiβe Anwendungen”, pp. 42-50, Elektronik 19 (1998)
L. Lorenz, M. März, G. Deboy, “Coole Leistungselektronik”, pp. 778-782, F&M 106 (1998)
L. Lorenz, M. März, H. Amann, “Robust Power MOSFET — A Milestone on the way to Simplified Circuit Technology.”, Elektronik, pp. 114-120 (1998)
L. Lorenz, M. März, “CoolMOS — a new approach towards high efficient SMPS solutions”, IMA Techno-Frontier Week 99, Japan.
L. Lorenz, G. Deboy, A. Knapp, M. März, “CoolMOS — a new milestone in a high voltage Power MOSFET”, ISPSD 1999, USA.
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