Designers that rely on Single-pulse Avalanche energy, EAS, alone for an application can be in for a surprise. This article will demystify this relatively unknown parameter that sheds light on the ruggedness of the MOSFET under avalanche conditions. It will provide an insight into how this parameter is calculated and measured and how it varies across different technologies.
Avalanche voltage ratings on datasheets have long mystified designers. Depending on circuit topology designers have often derated their MOSFET breakdown voltages by over 100% to ensure that they don’t run into avalanche issues on their FET. Datasheets ratings for values such at EAS (single pulse avalanche) and EAR (repetitive avalanche) are merely specifications at a particular test condition and by no means are an absolute rating. To understand avalanche, we need to understand the device physics behind the phenomenon.
Fig. 1a is the circuit model for a power MOSFET and Fig. 1b is a planar power MOSFET under avalanche conditions. Very simply put, all MOSFETs are rated for a certain max reverse voltage (BVDss). Operation above this threshold will cause high electric fields in the reverse biased P-N junction. This high electric field causes the creation of electron and hole pairs, resulting in increased current flow. By nature of the design of the structure of all MOSFETs, this current flow occurs near the base of the parasitic BJT present in all MOSFETs as shown in Fig. 1a and Fig. 1b. Current flow causes heating; heating causes silicon resistivity to increase and this in turn increases the base resistance RB . Ohm’s law dictates that a constant current across an increasing resistance causes a larger voltage drop across the resistor. Once this voltage drop gets large enough, it turns on the evil parasitic BJT, causing loss of control of the MOSFET.
As we know, all MOSFETs comprise many parallel cells that share current, but not all FETs are designed and tested similarly by all manufacturers, and in the absence of proper design and statistical testing, a parasitic failure of the BJT in one cell can cause destruction of the entire FET. However, an avalanche rugged MOSFET will only fail when the temperature greatly exceeds the rated TJMAX; hence it is even more important for designers to understand differences between FETs from various manufacturers.
Exercise care using datasheet EAS
It is important to note that datasheet EAS values from some manufacturers are thermally limited values - i.e. the device is rated to the value of EAS energy that causes an increase in junction temperature up to TJMAX which can be 150°C or 175°C. International Rectifier datasheets are rated in this manner unless explicitly stated in footnotes.
Many manufacturers use a statistical approach, i.e. devices are tested to the failure point and the value specified for the EAS on the datasheet is a statistical average of some kind. Now, because modern day avalanche tested MOSFETs can survive temperatures in excess of TJMAX (subject of course to thermal conditions of the package and environment), comparing datasheet values of EAS across manufacturers can be a misleading process for designers as it is not always clearly evident which methodology of EAS measurement the manufacturer is employing.
Many manufacturers adopt the single pulse UIS (unclamped inductive switching) tests to derive avalanche or EAS ratings for datasheets. This methodology is known, so let’s instead focus on work done at International Rectifier to characterize avalanche ruggedness across trench and planar generations that can help designers select MOSFETs.
Experimental Test Methodology
In order to better understand avalanche performance across trench and planar MOSFETs as well as newer and older generations of MOSFETs and knowing that MOSFET ruggedness depends heavily on test condition, device voltage, die size, and many other factors, we chose different generations of devices that have the same voltage-ratings, the same packages, and approximately the same die sizes to ensure silicon design generation is the sole factor of differences in the ruggedness performance.
The parts chosen for testing (Table 1) are all TO220 packages. Parts A1 to A5 are 100V rated with similar die sizes varying from 15.3 to 16.9 mm2; while parts B1 to B4 are 55V-60V rated, with similar die sizes varying from 5.3 to 6.2 mm2. Comparisons were made separately among the devices with the same voltage ratings. Note devices A1, A2 and B1, B2 are planar parts while the rest are trench parts. Also, the part letter and number labels indicate the technology, with A1 being older technology than A2 and so on.
Increase-to-fail Unclamped Inductive Switching (UIS) test was used for characterizing avalanche ruggedness in our evaluation. The test was done under eight conditions: two ambient temperatures (25°C and 175°C) and four inductors (20, 50, 100 and 500 μH). The detailed circuit and operation of the UIS tester can be found in application note [1]. A typical increase-to-fail UIS waveform is shown in Fig. 2. The part starts to operate at avalanche mode when the VDS exceeds its break-down voltage. The peak inductor current or IAS gradually increases till the part fails. The highest IAS at 20 μH, 25°C and 500 μH, 25°C are listed in Table 1.
For a rugged MOSFET without parasitic bipolar transistor effect, some references suggested that the avalanche failure is thermally induced. It occurs when the cell temperature reaches a critical value, beyond which the intrinsic carrier concentration exceeds the epi doping concentration [2]. Based on this understanding and the fact that the single-pulse thermal impedance curve of a MOSFET normally presents a constant slope in certain time ranges, we can conclude a linear relationship between IAS and the inductance (or between IAS and TAV, the avalanche time) in a log-log scale [3].
Fig. 3a-3b and Fig. 4a-4b separately compare IAS of parts A1-A5 and B1-B4 with respect to the inductance under two different ambient temperatures (25°C and 175°C). Fig. 3a and Fig. 3b suggest that 100V planar parts have much higher IAS with smaller inductors, exhibiting more robustness than their trench counterparts do; while with larger inductors, the difference between planar and trench parts is small. The dramatic fall-out of A3 and A4 (the two old trench technologies) in comparison to A1-A2 (the planar technologies) is most likely caused by the parasitic BJT, which is prone to turn-on at high currents. However, generation A5 shows a much improved avalanche rating compared to the earlier trench generations. In contrast, Fig. 4a and Fig. 4b show that, for 55-60V parts, planar and trench parts have very close avalanche performance under all tested conditions.
The results indicate that although the planar parts have better avalanche performance with smaller inductor sizes, as inductor sizes increase the avalanche performance is pretty similar for planar and trench parts. The results also indicate that newer generation trench platforms are much improved in their avalanche capability. A final observation is that avalanche capabilities are pretty similar at lower voltages amongst planar and trench devices.
Not All MOSFETs Are Created Equal
Datasheet parameters are merely first-pass selection criteria and should not be used by designers prima-facie. MOSFETs are subject to many stresses, and the designer needs to be aware of the parasitic inductances, as well as thermal limitations of the circuit board and environment as these can lead to unexpected MOSFET failures.
Recent literature [4] shows that even topologies such as the half-bridge, which were considered to be immune to avalanche owing to the clamping action of the opposing devices body diode, are susceptible to avalanche. Body diode recovery due to a rapid current turn-off can trigger avalanche in fast switching topologies, so designers need to carefully understand reverse recovery in conjunction to avalanche performance. Trench FETs typically have lower reverse recovery charge and hence for a given RDS(ON) perform better than planar parts, so avalanche due to reverse recovery on newer generation trench parts used in fast switching circuits is less likely.
Using a tight board layout and low inductance packages (such as DirectFET™), designers can minimize overall loop inductances that can cause large voltage spikes. Also, packages such as the DirectFET™ offer better dual-sided heatsinking options and more uniform thermal distribution across the die-surface that improves avalanche performance.
References
1. T. McDonald, M. Soldano, A. Murray, and T. Avram, “Power MOSFET Avalanche Design Guidelines,” Application Note AN1005, International Rectifier.
2. C. Blake, T. McDonald, D. Kinzer, J. Cao, A. Kwan and A. Arzumanyan, “Evaluating The Reliability Of Power MOSFETs,” Power Electronics Technology, 2005, pp. 40-44.
3. R. Stoltenburg, “Boundary Of Power-MOS, Unclamped Inductive-switching (UIS), Avalanche-Current Capability,” IEEE Applied Power Electronics Conference, 1989, pp. 359-364.
4. E. Persson, “MOSFET Failure Mechanisms During Fast Switching Events,” PCIM Europe, 2011
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