Despite silicon carbide’s (SiC) promise over conventional silicon for the design of next-generation power electronics devices, broad adoption of this high-performance compound semiconductor has been limited due to several perceptions concerning SiC substrate costs, the material’s physical idiosyncrasies, and the past challenge of controlling defect density.
Yet, none of these hurdles are insurmountable, and development of low-defect, large-diameter SiC wafers is now on the near horizon. So, it is worth exploring integration and design considerations for SiC as this cutting-edge material approaches commercial maturity.
SiC Cost Factors
To date, SiC device work is based on 76-mm and 100-mm diameter substrates. Compared to silicon devices made on 150- to 200-mm diameter wafers, the cost to manufacture devices on SiC substrates can be high, due to a combination of lower die count per wafer plus the additional costs to accommodate handling of smaller wafers in the manufacturing process flow. The recent advent of 150-mm diameter SiC wafers will reduce the manufacturing costs of SiC power devices by more than 50 percent, and eliminate costs in special handling. Fig. 1 shows a Dow Corning clean room technician inspecting both 150-mm and 100-mm SiC wafers.
The remaining question is whether or not SiC devices can be manufactured at a cost point that will yield a device product able to compete with silicon power devices in system applications. SiC’s properties enable design of power devices with smaller area or, put another way, devices designed for larger current density. This benefit provides the opportunity to populate the wafer with a larger number of dies compared to a conventional silicon power device design.
Obviously, as die count per wafer increases, costs should decline. Less obvious is that the relationship between substrate costs and device manufacturing costs does not scale directly when die size is a variable.
In simple terms for a fixed wafer diameter, the cost of the epiwafer (Wafer$) combined with the cost to execute the manufacturing and testing process (Fab$) represent the total manufacturing costs. Good manufacturing economics require that total costs taken relative to the number of dies per wafer should be a constant:
(Wafer$ + Fab$)/(Device Count) = Constant (1)
As the price of the wafer increases, Fab$ costs generally do not change. Yet, with higher wafer price, the cost to manufacture devices using SiC will also increase, unless a larger die count is achieved.
Consider the equation:
(Wafer1$ + Fab$)/(Device Count1) = (Wafer2$ + Fab$)/(Device Count2) = Constant (2)
The potential manufacturing throughput requirements of SiC can be estimated by considering the case for 150-mm wafer diameters. For this example, Fab$=1000, silicon wafer costs=$100 and the ratio of the SiC/Si wafer price cases are 20x, 10x and 5x. This example is close to that for a power transistor, and it illustrates the typical decline in new wafer price as use volume increases.
The right hand column of Table 1 indicates the fractional increase in the number of devices on a wafer, or the fractional reduction in die area of the SiC device necessary to achieve device fabrication cost parity with an equivalently specified silicon device. The properties of SiC, particularly its thermal conductivity, allow a device design strategy implementing a 2x reduction in die area. This calculation indicates that for Si and SiC, there can be a large differential in price between wafers of the same size, but the cost to fabricate devices can be comparable.
Impact of SiC Defects on Device Performance
Recent advances in SiC crystal growth have resulted in significant reduction of defects. Historically, the quality of new, larger wafers is relatively lower compared to prior generations, but it gradually increases over time with demand. While 150-mm diameter SiC wafers offer the opportunity to reduce the costs of SiC devices, they can still be an expensive platform for development. To take full advantage of 150-mm diameter SiC substrates, these substrates must be ready to support high production yields.
Defects in the larger diameter material must be maintained or improved to ensure that the performance of 150-mm diameter product technology will offer a seamless transition from smaller wafer diameters. Second, the performance of epitaxial film parameters and the device fabrication process must be sufficient to use the entire 150-mm wafer surface.
The known killer defect in SiC wafers is micropipes. As Dow Corning developed its crystal technology to achieve 150-mm crystals, low micropipe performance was maintained at <1/cm2. For larger devices, screw dislocations are of additional concern to many designers, and for bipolar device designs basal plane defects are a concern. In addition to achieving low micropipe density during expansions of crystals to 150-mm diameter, so far Dow Corning has have been able to continue low levels of both screw and basal plane dislocations. Table 2 shows the defects in SiC wafers 100 to 140 mm in diameter, comparing both screw and basal plane dislocations.
SiC device yield is also limited by surface defects generated during the chemical vapor deposition (CVD) epitaxy process. Today, this represents the defect most likely to limit or kill device performance. Current state-of-the-art in epitaxy defects depends on the film thickness target, and defect density of 1.5-2.0/cm2 is typical for wafers used in applications below 2 kV blocking voltage. Recent batch manufacturing epitaxy technology has been developed to accommodate the integration of 150-mm wafers. This capability will assure continuity in epitaxy defect performance between the 100-mm and 150-mm product generations.
Additionally, epitaxy capability can span both n- and p-type dopants and enable thickness ranges to >50 µm for high-voltage applications. These capabilities help promote 150-mm diameter substrate technology in all types of SiC device design strategies.
Design and Fabrication
Exploiting SiC’s high voltage and thermal conductivity properties compared to silicon is important to achieving successful device and system designs. Awareness of other properties of SiC wafers is also important in order to achieve successful device performance:
Transparency. SiC wafers are transparent, which can lead to some difficulty in photolithography utilizing steppers, in automated defect detection and in automated wafer handling. Automated defect detection may misidentify features below the surface as surface defects. In wafer handling, sensors set up for opaque materials may respond incorrectly, resulting in wafer breakage during load/unload events.
Dopant Incorporation. Implantation and activation of dopant atoms in SiC is more challenging than in silicon. Dopant diffusion is extremely small compared to silicon. In SiC, implant activation requires temperatures exceeding 1500 °C, and during this process the wafer surface must be adequately protected to prevent roughening. Activation efficiency may be lower than silicon, and total activation varies with the total dopant concentration.
Substrate Resistivity. SiC substrates have higher resistivity than silicon substrates. Since the epitaxy thickness used in SiC designs is small compared to silicon, the SiC substrate can contribute more to the series resistance of a device. Ohmic contact formation on SiC wafers often requires high temperature anneal (T> 800°C). This step must be performed early in the device fabrication flow, since the anneal temperature may be detrimental to subsequent device processes. Process optimization is important to assure series resistance effects resulting from the ohmic contact are minimized, and optimum low forward voltage drop performance in SiC diodes and metal-oxide semiconductor field-effect transistors (MOSFETs) is achieved.
Defects. The most critical defect associated with SiC devices are polycrystalline surface defects that form on the wafer surface during epitaxy. These killer defects are easily detected with automated optical spectrometry techniques. Surface protrusion from defects can lead to comet formation in photoresist layers, and result in fabrication failures in areas of the wafer away from the defect. Inspection of photoresist is an important in- process step to identify potential fabrication issues. Other defects can also be present that can limit the performance of devices. Very light damage from polishing processes can result in shallow linear defects on the epitaxy surface that will become decorated during metallization steps. These defects can lead to hot spots on the device in the region under the gate or in the edge termination areas.
Device Attributes. SiC devices like Schottky diodes and MOSFETs exhibit positive temperature coefficients for the forward bias on state resistance. Many results have been reported in the literature and the device suppliers’ application notes that SiC devices exhibit lower conduction losses and switching losses compared to silicon-based devices. There are many models used when designing SiC devices. But the models, while improving, still show offsets from experimental data measured on fabricated devices. Care should be made to ensure materials properties entered in the model are consistent with those of the materials used to fabricate the devices. The model should be evaluated such that it reflects internal wafer and wafer-to-wafer variations of the substrate and epitaxy to provide leading indication of the distribution of results.
Through numerous collaborations and partnerships focused on the materials characterization and device fabrication, expertise in product specification and applications development can accelerate the efforts of semiconductor device manufacturers to implement SiC in next-generation power devices and systems.
References:
- M.J. Loboda, G. Chung, E. Carlson, R. Drachev, D. Hansen, E. Sanchez, J. Wan, J. Zhang, “Advances in SiC Substrates for Power and Energy Applications,” CS MANTECH Conference Digest, presented at Compound Semiconductor MANTECH Conference, May 16th-19th, 2011, Palm Springs, California.
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