eGaN® FET-Silicon Power Shoot Out Volume 12: Optimizing Dead Time

Jan. 3, 2013
Significant efforts have been made to show the performance improvements achievable with eGaN® FETs over silicon MOSFETs in both hard and soft switching applications. This volume of the eGaN FET-Silicon power shoot-out series continues to examine the optimization trend and look at the impact of dead-time on system efficiency for eGaN FETs and MOSFETs.

Initial shoot-out articles [2, 3] showed that eGaN FETs behave similarly to silicon devices and can be evaluated using the same performance metrics. Although eGaN FETs perform significantly better by most metrics, the eGaN FET ‘body-diode’ forward voltage is higher than its MOSFET counterpart and can be a significant loss component during dead-time. Body diode forward conduction losses alone do not make up all dead-time dependent losses. Diode reverse-recovery and output capacitance losses are also important. We will discuss dead-time management and the need to minimize all dead-time losses.

To start, consider the reverse transfer characteristics for both MOSFETs and eGaN FETs, shown in Fig. 1. This figure shows a 1.5 V increase in forward voltage drop of the eGaN FET ‘body diode’ compared to a Si MOSFET at 25°C, as temperature increases the voltage difference increases to almost 2 V. What isn’t shown is that since the eGaN FET ‘diode’ is just the channel conducting in reverse and a majority carrier operation; this results in no diode reverse-recovery charge in eGaN FETs. Body diode forward conduction and reverse recovery losses are not the only dead-time related losses; there are output capacitance losses and additional switching losses when the self-commutation time is longer than the allotted dead-time.

Effective Dead-Time

For this analysis presented, effective dead-time will be used. The effective dead-time is defined from when one device reaches turn-off threshold (VTH) voltage on the gate to when the other device, which is turning on, reaches its threshold voltage. For a constant controller dead-time, the effective dead-time depends on variations in device threshold voltage, gate resistance, and gate capacitance. The resultant effective dead-time also depends on device operating voltage and the pulse-width variation in the gate drive circuit.

There are only a limited number of ways to have the body diode conduct during dead-time period. To determine the effect of gate timing on body diode losses, all of these device states will be considered. In simple terms, there is the possibility for body diode conduction at both turn-on and turn-off of a device. To have diode conduction at device turn-off, a negative current must be flowing from source to drain (positive current defined as flowing drain to source), such as the turn-off of a synchronous rectifier in a buck converter. For negative currents (diode conduction at device turn-off), the next device turn-on will always be hard switching and require reverse recovery of the conducting diode. There is some evidence [4, 5] to suggest that the reverse recovery losses in MOSFETs can be reduced by limiting the commutation time of the body diode, but much of this depends on the MOSFET diode forward recovery, which is not available. In most cases, the current commutates fully to the body diode, resulting in eventual diode reverse recovery and more dead-time.

For diode conduction at turn-on, the drain voltage across the device turning on must be externally commutated by a positive current flowing into of the drain terminal, such as the dead-time interval before the turn-on of a synchronous rectifier in a buck converter. For such positive currents, the analysis is more complex as drain voltage across the turn-off device starts increasing and is load current dependent. If there is enough energy in the inductor to commutate the voltage completely, lossless zero voltage switching (ZVS) turn-on can be achieved, but increasing dead-time further will only incur additional diode conduction losses. Reducing dead-time below that required for ZVS will cause hard-switching at reduced switching voltage and will also increase losses. Thus, for positive currents, there are load current dependent optimum effective dead-time values. Fig. 2 shows the full range of drain to source voltage waveforms for both negative and positive currents for a given dead-time. The waveforms are color coded to represent relative dead-time dependent commutation loss, from maximum loss (Dark Red), down to pure lossless commutation (Blue).

For this analysis, the switching loss at both turn-on and turn-off are neglected, as these are not dead-time dependent. But, as discussed above, it is possible to incur additional synchronous rectifier hard-switching turn-on losses for positive currents where dead-time is insufficient to allow commutation. Additionally, body diode conduction, output capacitance losses (EOSS), and diode reverse recovery losses (EQRR) are considered. The special case of zero-current turn-off is also shown. In this case, the zero-current switching (ZCS) turn-on will incur only EOSS losses.

To optimize efficiency and minimize dead-time commutation losses, different load current ranges at both turn-on and turn-off dead-time intervals are important. The range of the dead-time commutation waveforms shown in Fig. 2 is meant to be exhaustive and will be much larger than needed for most specific applications and specific dead-time intervals. Since we need to compare eGaN FETs and silicon MOSFETs over a wide range of voltages and applications, the whole load current range of Fig. 2 will be considered. It will then be possible to select a subset of these for a specific application dead-time interval and determine the required optimization conditions for it. To represent the wide range of possible dead-time losses and quickly compare FET technologies, Fig. 3 shows a graphical representation of the energy loss as function for the whole range of currents. The specific dead-time value used in Fig. 2 becomes a single point along the x-axis with each commutation waveform resulting in a separate energy loss number (colored circles).

For this analysis, two devices in a half-bridge (totem-pole) configuration are assumed and reduced voltage hard-switching turn-on, output capacitance, body diode and reverse recovery losses are calculated using equations from Table 1 of [1] and calculating the parameters from the respective device datasheets. These equations are repeated in Table 1 and rewritten to accommodate reduced voltage switching and energy loss per dead-time interval calculation.

eGaN FET - MOSFET Comparison

The dead-time losses in a 60 V bus half-bridge application using 100 V eGaN FETs [6] and similar RDS(ON) state of the art 80 V MOSFETs [7] are shown in Fig. 4. The lines are drawn in 4 A load steps from –20 A to +20 A. The comparison clearly shows the following differences:

  1. Self commutation times for eGaN FETs are about half as long as those of the MOSFETs due to lower output capacitance.
  2. Stored energy losses and diode reverse recovery losses in eGaN FETs are 36% that of MOSFETs due to lack of reverse recovery and lower output capacitance.
  3. Body diode conduction loss increases with time in eGaN FETs is about 2.5 times faster than MOSFETs due to the higher diode conduction voltage.
  4. Optimum dead-time range depends on load current, but with the eGaN FETs, this range is about 50% that of the MOSFET.

For practical designs where a single dead-time is used for all load current conditions, the values might be 20 ns ±7 ns and 44 ns ±16 ns respectively and would yield similar sub 1 mJ dead-time loss results (areas highlighted in orange in Fig. 4). Lower dead-time losses are possible, but would require tighter tolerances and/or dynamic dead-time optimization.

In lower voltage applications, the effect of the body diode is more pronounced relative to other losses. Consider such a 12 V buck application using 40 V eGaN FETs [8] and similar RDS(ON) state of the art 30 V MOSFETs [9] with dead-time losses (Fig. 5) The lines are again drawn in 4 A load steps from -20 A to +20 A. The comparison is similar to the 60 V case except for comparison numbers 2 and 4, which have the following differences:

2. In eGaN FETs, hard commutation stored energy losses and diode reverse recovery losses have increased to 45% relative to that of MOSFETs.

4. Optimum dead-time range is still about 50% that of MOSFET, but both are much smaller. (The 4 A to 20 A eGaN FET dynamic optimum range is just 3 to 6 ns vs. 7 to 13 ns for MOSFETs). For a constant dead-time design, both dead-time ranges (Fig. 5) are less than 6 ns wide and may be difficult to generate this required accuracy. Lower dead-time losses are plausible, but would require even tighter tolerances and/or dynamic dead-time optimization.

Given the current lack of capability for such tight tolerances for most MOSFET driver and MOSFET combinations, a common alternative solution to such a small dead-time range is to minimize dead-time losses over a more realistic range by adding a parallel Schottky diode. In silicon, this is only effective when the Schottky diode is monolithically integrated into the MOSFET, as the small voltage drop difference between the body diode and Schottky diode together with the large loop inductance between them would mean a too long commutation time to be practical [10]. Furthermore, partial commutation to the Schottky diode would mean that the MOSFET body diode would still have to recover at turn-off with the additional associated recovery losses. Alternatively, lengthening the diode conduction time to allow complete commutation will incur additional diode conduction losses instead.

For eGaN FETs, the case is very different. First, there is no body diode reverse recovery, so even with partial current commutation from the body diode to the Schottky diode it would still reduce overall dead-time losses.

Second, the much higher body diode forward drop is actually beneficial for the addition of a Schottky diode here as it increases the current commutation speed by generating a larger voltage differential between the two diodes [11].

Third, the low parasitic inductance of the eGaN FET’s land grid array (LGA) package makes the addition of an external Schottky diode possible by reducing the commutation loop inductance. Care should be taken to minimize the Schottky diode package inductance and pcb loop also to avoid negating this advantage. This is best done by placing the Schottky diode next to the eGaN FET on the same side of the board and choosing a low inductance package Schottky [12, 13]. The improved thermal package parts with exposed tab are good as they remove one or both wire-bond connections. A suggested layout is shown in Fig. 6.

Following the same loss calculation, the effect of adding a 3 A Schottky diode to the eGaN FET in a 12 V application can be seen in Fig. 7 (right) compared to the standard eGaN FET with no Schottky diode (left). We can draw the following conclusions:

  1. Adding a Schottky diode increases output capacitance losses and lengthens self-commutation time. Choosing the right size Schottky diode is important to balance the capacitive loss increase with reduced diode conduction losses.
  2. The diode conduction losses are decreased to about 40% for a 3 A Schottky diode and are in direct relation to the decrease in the forward diode conduction drop. Optimal scaling of the Schottky diode can improve this for a selected load range.
  3. The practical dead-time range (for <0.2 mJ losses) is increased almost four times and is almost twice than that of the equivalent MOSFET diode without the integrated Schottky diode in Fig. 5.

Experimental Verification

To determine if an external Schottky can actually be used, two equivalent buck converter boards were built using 40 V eGaN FETs and equivalent 40 V silicon MOSFETs, both converters were operated at 1 MHz, 12 VIN and 1.2 VOUT. Effective dead-time at both edges were set equal and the load was swept up to 20 A. The tests were then repeated with a 1 A external Schottky diode added. Fig. 8 shows the measured results. For optimum effective dead-time, the dead-time is adjusted to eliminate body diode conduction, while for 5 ns and 10 ns dead-time, the gate timing is adjusted for a constant effective dead-time as per Fig. 2.

From Fig. 8, the following results can be seen:

  1. At this low power level and high frequency operation, every 5 ns of effective dead-time per edge (10 ns total per cycle) incurs a 1% drop in efficiency.
  2. Adding even a small external Schottky diode will significantly reduce the dead-time losses by as much as 70% around 10 A load and more than 50% overall. The decrease in improvement at higher output currents is due to the higher Schottky diode forward drop at the high currents. As such, the deliberately chosen 1 A diode [14] is undersized for such a 20 A output application. Using a larger Schottky diode will move the peak efficiency improvement to higher output currents.
  3. Even with an undersized external Schottky diode with forward drop greater than 1 V at 20 A [13], the circuit is still capable of commutating current and reducing the overall dead-time losses by about 50%.
  4. For the MOSFET design, the external Schottky diode shows no measurable improvement and emphasizes the fact that an integrated Schottky diode is needed to reduce the effective dead-time losses.
  5. The eGaN FET design needs to have either about half the effective dead-time of the MOSFET design or an external Schottky diode with the same effective dead-time, to have similar dead-time losses.

In general, eGaN dead-time needs to be about half that of MOSFETs, but the significance of this loss component decreases with increasing bus voltage, while at lower voltages the use of an external Schottky diode can reduce dead-time losses by up to 70%.


[1] J. Strydom, “eGaN® FET- Silicon Power Shoot-Out Volume 11: Optimizing FET On-Resistance”, Power Electronics Technology, Oct. 2012, http://powerelectronics/discrete-semis/gan_transistors/egan-fet-silicon-power-shoot- vt.ed out-volume-11-optimizing-fet-on-resistance-1001/ .
[2] J. Strydom, “eGaN® FET-Silicon Power Shoot-Out Part 1: Comparing Figure of Merit (FOM)”, Power Electronics Technology, Sept. 2010,
[3] J. Strydom, “The eGaN FET-Silicon Power Shoot-Out: 2: Drivers, Layout”, Power Electronics Technology, Jan. 2011,
[4] J. Cerezo, “Class D Audio Amplifier Performance Relationship to MOSFET Parameters”, International Rectifier application note, AN-1070.
[5] M. Christian, “Improving Efficiency of Synchronous Rectification by Analysis of the MOSFET Power Loss Mechanism”, Infineon Technologies Application Note, AN-2012-03.
[6] EPC2001 datasheet, EPC Corporation, eGaNFETs/EPC2001.aspx.
[7] BSC057N08NS3G datasheet, Infineon Technologies.
[8] EPC2015 datasheet, EPC Corporation.
[9] BSC034N03LS datasheet, Infineon Technologies.
[10]J. White, “MOSFET Body Diode”, Hephaestus Audio.
[11]D. Reusch, “High Frequency, High Power Density Integrated Point of Load and Bus Converters,” Ph.D. Dissertation, Virginia Tech, 2012.
[12]Diodes Incorporated news release, “Diodes, Inc. Introduces Industry-Leading High Efficiency SBR Devices in PowerDITM123 Compact Power Package”, January 2007.
[13] Panasonic news release, “High Thermal Dissipation Schottky Barrier Diode with Ultra-Small PMCP Package”, September 2012.
[14]MSS1P4 datasheet, Vishay.

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eGaN(tm)-Silicon Power Shoot-Out: Part 1 Comparing Figure of Merit (FOM)

Commercial 600V GaN-Based Power Devices Coming of Age

Characterizing High Power Semiconductors Requires New Technologies

Quality, Robustness and Reliability of 600 V GaN-on-Si Power Devices


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