3D-Integrated MOSFETs With Ultra-Low DCR Inductor Provides High-Efficiency DC/DC Regulator

High-density efficient power management is increasingly critical in a broad range of applications. As the available PCB real estate in server, networking, base station, and enterprise computing applications becomes more confined, and given the proliferation of voltage rails in these systems, DC/DC voltage regulators need smaller form factors, scalability, and lower cost. High conversion efficiency is the overarching requirement as this clearly translates into lower power loss and less package temperature rise. It enables a high power-density form factor and, when coupled with optimized thermal performance, high useable power for a given airflow and ambient temperature environment. In light of the foregoing, the ascendant interest in accurate and lossless current sensing as a key attribute in these designs is directed towards:

1) Output current limit (short-circuit/overload protection (prevent inductor saturation)

2) Current-mode control

3) multi-phase current sharing

4) adaptive voltage positioning (AVP) in microprocessor applications

5) load current telemetry and monitoring

Measuring current in DC/DC regulators

Using the intrinsic circuit parasitic elements, like inductor dc resistance (DCR) or MOSFET on-state resistance, for lossless current sensing is quite common as it enables high-power density and low-cost circuit implementations. But merely sensing the voltage across the low-side MOSFET in a buck converter is inaccurate, given the large initial tolerance of the R_DS(ON) (as high as ±30%) and the variation with temperature inherent with the MOSFET die. Also, sensing is possible only when the low-side MOSFET is conducting. By contrast, the tolerance of an inductor’s DCR typically is specified at ±8%, sometimes even lower. The inductor DCR current sense technique, shown in Fig. 1a by connecting an RC filter network in parallel with the inductor, is widely adopted in DC/DC regulators for point-of-load (POL) applications.

Fig. 1. Two current sensing scenarios: (1a) synchronous buck with conventional inductor DCR current sensing; (1b) proposed current sense circuit availing of vertically integrated MOSFET structure to increase sensed signal amplitude. The parasitic resistances are represented as lumped circuit elements.

By closely emulating the inductor admittance with a low-pass sense network, a proportional voltage image of the inductor current is derived. From Fig. 1, the sense capacitor voltage in the Laplace domain is given by Equation 1.

A flat frequency response is achieved when the inductor time constant matches that of the RC sense network. So, a differential measurement of the sense capacitor voltage is a mirror image and accurately reveals the instantaneous inductor current, both in steady state and transiently. Time constant matching and DCR temperature coefficient are also important considerations ^{[1, 2]}.

The trend towards higher switching frequencies and the need for fast-load transient response means that a relatively small inductance is feasible. At high-output currents, ultra-low DCR ferrite inductors offer lower copper and core losses. Unfortunately, the current sense signal amplitude derived from sub-mOhm inductor DCR is quite low. For example, a 30-A full-load current with 0.25-Ohm DCR produces only 7.5 mV at room temperature, driving the need for low-offset circuits to meet accuracy specifications. With the hard saturation characteristic of ferrite-cored inductors, the imperative is to avoid exceeding the inductor’s saturation current threshold. No wonder, then, the exigency is to harness other power train parasitic resistances to boost the available signal level. Paramount is maintaining compatibility with the typical voltage differential measurement techniques commonly used in commercial dc/dc regulator controllers with inductor DCR current sensing ^[1].

Integrated Power MOSFET

Illustrated in Fig. 2 is TI’s NexFET^TM Power Block, a half-bridge arrangement of two MOSFETs using 3D device structure and package integration techniques. Co-packaging of high- and low-side power MOSFETs reduces parasitic inductances, thereby improving switching performance. Using a system-optimized grounded leadframe, thick copper clips for input (V_IN) and switch (SW) power connections, and vertical die-stacking, the asymmetric MOSFETs are optimized for low duty cycle operation, efficiency and high-power density in high-switching frequency applications ^[3].

As shown in Fig. 1b, an increased effective sense resistance (and resultant voltage signal amplitude) is realized by advantageously employing the package structure copper resistance in the vertically-integrated MOSFET device. Here, the inductor DCR current-sensing method is remodeled to include the copper resistance of the MOSFET’s switch clip, connecting high-side source and low-side drain.

Fig. 2. Vertically integrated power MOSFET structure. 3D integration results in extremely low parasitics and efficient, high-frequency operation.

With the MOSFET construction as shown in Fig. 2, the return to the high-side gate driver, T_GR, is a kelvin connection attached to the drain of low-side MOSFET (and not source of high-side MOSFET, as typically expected). The voltage drop across the switch copper plate is now easily sensed and incorporated with the sensed voltage from the inductor DCR. The cumulative signal derived from the DCR and switch plate offers a continuous signal at higher amplitude, thus facilitating accurate current sensing performance. From Equation 2, the effective sense resistance on an average basis is the DCR, plus the clip resistance weighted by the pulse-width modulation (PWM) duty cycle, and the sense network time constant is chosen accordingly.

This aligns well with low-duty cycle, high-current buck regulator applications (for example, 12V input to below 1.8V output). By virtue of the parasitic sensing elements comprising copper, temperature compensation is straightforward.

Circuit Simulation

Fig. 3. Buck regulator simulation schematic.

The current sensing technique just described is investigated with the circuit simulation schematic presented in Fig. 3. The operating conditions and key component values listed reflect the practical circuit implementation discussed next. Fig. 4 is a time domain simulation result of a 10-A load step transient response at 10 A/ms showing the instantaneous inductor current and sense capacitor voltage waveforms. Here, the sense network time constant is based on a 1-mOhm effective sense resistance and 10% PWM duty cycle. The blue trace in Fig. 4 is an accurate representation of the inductor current is achieved.

Fig. 4. 10-A load step response simulation with output voltage and current, inductor current and sense capacitor voltage.

Implementation And Experimental Results

An example of a high-density, 600-kHz regulator implementation ^[4] is shown in Fig. 5. The power stage comprises TI’s CSD87350Q5D Power Block MOSFET, a 300-nH ferrite inductor with 0.29-mΩ DCR, and ceramic input and output filter capacitors. The design uses a LM27403 PWM controller to provide overcurrent protection using the hybrid current sensing method outlined above. The current limit setpoint is set at 30 A. Change in copper sense resistance with temperature is compensated by the PWM control IC’s remote temperature sense capability. This generates a concomitant change in current limit threshold voltage with temperature. A 2N3904 BJT located adjacent the powertrain component hotspots is used as a temperature sensor. The sensor is positioned closer to the MOSFET, if the MOSFET is expected to sustain a larger temperature increase than the inductor. Using the top gate return (TGR) connection instead of a switch actually simplifies PCB trace routing in this design.

Fig. 5. 20 mm x 14 mm DC/DC regulator.

With the common source inductance of the high-side MOSFET essentially eliminated by kelvined gate connections, low MOSFET charge parameters enable reduced switching losses. Leveraging the heat spreading advantages of the grounded tab, total MOSFET power dissipation at 25-A output current is approximately 2W.

Off-the-shelf component options for low DCR ferrite inductors with single-turn “staple” winding are widely available, see Table 1 for some examples. Inductor power dissipation at 25 A, including copper and core loss at 75°C operating temperature, is 0.5W.

Fig. 6. Measured efficiency for 12-V input and 25 Â°C ambient temperature.

Various experimental measurements, including efficiency and current limit, are recorded to evaluate circuit performance. The measured efficiencies at various output voltages are shown in Fig. 6. Current limit performance data is collated in Fig. 7.

Fig. 7. Measured current limit inception at 12-V input.