Optimizing Output Capacitance When Using PoL Converter Modules

Point of Load (PoL) dc-dc converter modules provide regulated dc power to a wide variety of loads. PoLs are small, efficient and relatively inexpensive, so their ability to provide common powering voltages to groups of semiconductor and IC loads has resulted in their adoption by circuit board designers for many applications.

As the complexity of today's board designs continues to expand, the number of individual voltages required to properly power all the IC loads on a board increases, ranging from three to 10 voltages or more. To address this need, on-board power architectures that combine isolated dc-dc converters or ac-dc power supplies with PoL converters are now the best-practice approach.

As the number of board voltages has proliferated, the ICs likewise have become more demanding. Already at sub-1-V levels, the new generation of silicon demands ever-tighter voltage regulation for optimum performance. Compounding this, designers strive to add more functionality into the same silicon while attempting to maintain the power draw. The result of lower voltages at the same level of power consumption results in a marked increase in current requirement. An IC that operates at 20 W maximum power consumption would draw 11 A at 1.8 V, but draws 20 A at 1 V. This is just one implication of the reduction in powering voltage; there are more severe aspects to consider.

PoL OUTPUT REGULATION CHALLENGES

To achieve proper performance, IC manufacturers typically impose tight limits on the supply voltage variation that may be tolerated. A typical specification is that the voltage may not deviate by more than ±5%, and might even be as tight as ±3%. As the powering voltages drop, these tolerances translate into ever-tighter bounds. A ±5% band at 1.8 V is 180 mV, but at 1 V, it is only 100 mV.

PoLs powering ICs must maintain this tolerance under varying input voltage, load current, temperature, component variations, and drift over the life of the product. Fig. 1 outlines this challenge. The upper and lower bounds for the supply voltage are imposed by the IC being powered. The total deviation consists of three components:

1. Static deviations (variation of the PoL average voltage due to component tolerances, temperature, line, and load regulation).
2. PoL switching output ripple.
3. Dynamic voltage variations due to transient load changes.

Typically, you can use a budgeting process to allocate the entire allowed voltage deviation window among various contributing factors. For example, out of a total band of 10% of the nominal powering voltage the worst-case static deviation may be 3%, output ripple may be 1% and with a 2% safety margin — leaving 4% for transient deviation. The actual transient deviation allowed for a minimum to maximum load-current change would then be half of the 4%, or 2%. At 180 mV this translates to 36 mV; at 1 V it drops to 20 mV. Referring back to the current draw on a 20-W load, a 50% transient load change at 1.8 V translates to 5.6 A, but at 1 V, it becomes 10 A.

As powering voltages drop, the voltage-deviation tolerance shrinks while the load step increases. The cumulative effect is to end with a problem that is more than twice as difficult (1.8x-higher current step / 0.56x specified deviation band).

Historically, the solution to improving the transient response of PoLs has been to increase the capacitance placed across the output of the PoL module. The additional energy storage provided by the capacitors reduces deviation in the output voltage during a transient load step.

The implications, however, are increased cost, increased board area, and reduced reliability. Furthermore, this brute-force solution eventually runs out of steam and begins to degrade the transient response, causing an increasingly sluggish recovery time. Finally, this approach hits a hard limit where adding more capacitance results in lower stability margins and eventually the full onset of instability.

THE TUNABLE LOOP FEATURE

The traditional solution to improving the transient response by adding more capacitance is illustrated in Figs. 2a and 2b. For example, the figure illustrates the response of a Lineage PicoTLynx ^™ 6-A PoL module at a 1.8-V output with a 50% load step (3 A) using a single 47-µF capacitor (Fig. 2a) and then using two 47-µF capacitors (Fig. 2b). Clearly, there is an improvement, but it falls far short of optimizing the response to a load transient.

The Tunable Loop feature ^[1], patented by Lineage Power, provides an answer. Fig. 2c demonstrates the substantial improvement afforded through the implementation of the Tunable Loop. Clearly, with the tightening budget on voltage deviation and increasing load step demands, the immediate impact of this technology is apparent.

The output voltage response by PoLs is a function of two parameters: the external capacitance, and the control bandwidth of the PoL+load. Fig. 3 illustrates the role of external capacitance in reducing the output-voltage deviation due a transient load change. The PoL's limited bandwidth (typically the control-loop gain crosses through the 0-dB point at no more than 1/6 the switching frequency) causes the initial surge of current needed during a load-current step increase. The external capacitors support this surge.

Once the PoL control loop is comes into play, the PoL provides this new level of load current, and the current from the external capacitor approaches zero. Hence, external capacitors improve transient voltage response by providing additional energy during the transitions between load current levels. As external capacitance is added, the initial voltage deviation due to a load transient is reduced further, leading to the conclusion that lower transient voltage deviations are achieved simply by adding more capacitance.

The PoL control bandwidth is the other parameter that controls transient deviation. Fig. 4 illustrates that as the control bandwidth increases; the transient response improves for a fixed external capacitance. Consequently, it can be seen that as long as stability is maintained, increasing control bandwidth continues to improve transient response.

Although increasing control bandwidth and increasing the external capacitance both improve transient response, these parameters are not independent. In fact, there is a strong interaction between them, so that simply increasing the external capacitance degrades the control bandwidth of the system. Therefore, the full benefits of the additional external capacitance cannot be realized unless this degradation is counteracted. That is the function of the Tunable Loop feature. It allows the designer to re-tune the control loop through components connected external to the module to compensate for the additional external capacitance, resulting in an optimum balance of capacitance and bandwidth and yielding the best transient response possible for a given set of application requirements.

The power of the Tunable Loop is in its simple implementation. As depicted in Fig. 5, an external network comprising a resistor and capacitor in series is connected across the TRIM and V _OUT (or SENSE) pins of the PoL module. These are typically very small, inexpensive passive devices. The resistor may be size 0805, 0603, or 0402 SMT components in resistances from a few ohms to a few kilohms. Likewise, the capacitor is similar in size, ranging from a few hundred picofarads to a few hundred nanofarads. Fundamentally, this allows a single standard PoL module to be externally optimized across multiple applications of significantly varying demands with minimal effort yielding the optimum board area, cost, response, and reliability. This additional benefit of module consolidation through a simple programmable feature yields significant dividends on both technical and commercial levels.

EXAMPLE TUNABLE LOOP CONVERTER

Let us consider the example of a 12-V Pico TLynx^™ 6-A converter. Through simulation models, we can easily examine both the transient response and control-loop behavior. First, let's consider the impact of adding more capacitance.

Fig. 6 illustrates the converter's transient response to a 50% (3-A) load step at different levels of external capacitance (0, 1×47 µF, 2×47 µF, 3×47 µF). Note that while the maximum voltage deviation does improve from 415 mV (no capacitance) to 235 mV (3×47 µF), the control-loop bandwidth drops from 78 kHz to 21 kHz. This can also be noted in the increased sluggishness of the voltage recovery, so that while adding capacitance does reduce the peak voltage deviation, it simultaneously increases the duration of the voltage excursion. This is consistent with the reduction in control bandwidth and poorer phase margin caused by the increasing capacitance.

The ultimate goal is to regain the bandwidth lost due to the increased capacitance through the use of the Tunable Loop feature. To demonstrate the process, we fix the value of Rtune to 150 Ω and vary Ctune from 0 pF to 7,500 pF. Fig. 7 illustrates that increasing Ctune correspondingly increases the control bandwidth from 21 kHz (Ctune=0 pF) to 82 KHz (Ctune=7,500 pF). The Tunable Loop has recovered and even exceeded the lost bandwidth, but the true benefit is evident as the voltage deviation improves from 235 mV to 49 mV. Note that the voltage waveform also settles much faster and without overshoot. In this example, the Tunable Loop achieves a 4.8x voltage deviation reduction at the same level of output capacitance.

Alternately, the Tunable Loop can achieve a lower voltage deviation specification with a significantly reduced capacitance. Fig. 8 graphically demonstrates the size and cost reductions obtained by using the Tunable Loop in another design, where the 6-A Pico TLynx module is used to power an application from 5 Vin to 1.2 Vout at 4 A, with a maximum step load of 3 A and a required output voltage deviation not to exceed 4% (48 mV).

For the case where the Tunable Loop is not used, three polymer electrolytic capacitors are required, whereas when the Tunable Loop is employed, only three ceramic capacitors are needed, resulting in a $0.60 reduction in external capacitor cost and a drop in required PWB space of 111 mm² (0.173 in²). Since the module itself occupies only 149 mm², the total board area reduction is very significant.

Greater reductions in cost and board area due to external capacitance can be achieved with higher-current modules. Fig. 9 shows graphs of output capacitance vs. output voltage deviation for a 40-A module, where a 10-A step load is applied.

In addition to the reduction in output capacitance that the Tunable Loop provides, the range of external capacitance that can be attached to the module is about six times larger than without tuning. This powerful capability also enables the use of much larger values of external capacitance with PoLs when either very low values of output ripple are needed or extremely small transient voltage deviations are required.

While the cost and board-area savings are significant, another benefit of using fewer capacitors (and potentially only ceramic capacitors) is higher reliability. The simple tools made available in the configuration of the Tunable Loop parameters also lead to better-characterized and more robust designs that can increase the likelihood of “getting it right the first time”.

Where design parameters are susceptible to change, stability characteristics can likewise change. An example of this is capacitor ESR variation due to variability in procurement. Having the flexibility to change and tune the dynamic characteristics of the design via the Tunable Loop components provides a powerful level of robustness.

The Tunable Loop is shown to be a powerful technique that helps designers optimize the amount of external capacitance needed when employing standard PoL modules (Fig. 10). In addition, Lineage Power has licensed the Tunable Loop technology to Murata Power Solutions and Bel Fuse Inc., providing a set of second-sourced parts.

Data sheets for these modules provide an initial set of recommended values of Ctune and Rtune for a range of applications. Simulation models and selection tools for all converters that support a wider range of optimization choices are also available and these provide additional benefits in being able to predict design performance before committing to hardware.

REFERENCES

1. TUNABLE LOOP PATENT APPLICATION

   Thomas G. Wang, Vijayan J. Thottuvelil, Cahit Gezgin, “Circuit and Method for Changing Transient Response Characteristics of a DC/DC Converter Module”, U.S. Patent 7,432,692, 2008.

Tunable Loop Patent Application

United States Patent
7,432,692

Wang, et al.
October 7, 2008

ABSTRACT

Circuit and method for changing transient response characteristics of a dc-dc converter module

A circuit for, and method of, changing transient response characteristics of a dc-dc converter module having an output-rail pin and a trim pin and a distributed-power conversion system incorporating the system or the method. In one embodiment, the system includes a reactive component coupled to the output-rail pin and the trim pin of the dc-dc converter module and configured to interact with at least one network internal to the dc-dc converter module to change the transient response characteristics.

Inventors: Wang; Thomas G. (Fremont, CA), Thottuvelil; Vijayan J. (Addison, TX), Gezgin; Cahit (Murphy, TX)

Assignee: Lineage Power Corporation (Mesquite, TX)

Appl. No.: 11/558,004

Filed: November 9, 2006