High Efficiency PoE++ PD Controllers Deliver up to 90W

Nov. 5, 2012
The desire for higher power delivery has grown along with the number of Power over Ethernet (PoE) applications. Now, Linear Technology’s LTPoE++™ standard satisfies this desire by extending the PoE and PoE+ specifications to 90W for the powered device (PD).

PoE systems employ Power Sourcing Equipment (PSE) to send DC power and data over Ethernet cables to a remote Powered Device (PD), as shown in Fig. 1. This frees the PD from having to employ AC line power. Originally, PoE systems were based on IEEE 802.3af that allowed 13W for the PD. Then, there was an update to PoE+ (IEEE 802.3at), limiting the maximum PD power delivery to 25.5W.

Unfortunately, the present IEEE 802.3at standard does not provide enough power to handle the new class of power-hungry applications, such as Picocells, base stations, signage, and heated outdoor cameras. Now ready to fill this power gap is Linear Technology’s LT4275 that can deliver up to 90W for powered devices. Designated LTPoE++, it expands the power available at the PD to four different power levels: 38.7W, 52.7W, 70W and 90W. Linear’s LTPoE++ standard employs a classification scheme that simply enables LTPoE++ PSE controllers and LTPoE++ PD controllers to reliably communicate with one another while maintaining interoperability with existing IEEE standard equipment.

Three LT4275 PD controller versions deliver power to loads using just one IC, as shown in Table 1.

Most of the older generation PD controllers utilize an on-chip power MOSFET switch. In contrast, the LT4275 controls an external MOSFET, which reduces overall PD heat dissipation and maximizes power efficiency – an important feature at higher power levels. A low RDS(ON) MOSFET also maximizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. This configuration allows designers to size the MOSFET to their application’s specific heating and efficiency requirements. An internal charge pump allows an external N-channel MOSFET solution and eliminates the need for a larger and more costly P-channel FET.

LTPoE++ PSEs can differenti­ate between an LTPoE++ PD and all other types of IEEE compliant PDs, allowing LTPoE++ PSEs to remain compatible and interoperable with existing equipment. Any high power allocation scheme violating the IEEE-mandated detection resistance specifications risks damaging and destroying non-PoE Ethernet devices such as NICs.

Standard PoE PSEs use two of the four available Ethernet cable pairs for power, as shown in Fig. 1. Some power-extending topologies use two PSE controllers and two PD controllers over one cable to deliver 2 × 25.5W. This strategy doubles the number of compo­nents, which doubles PSE and PD costs. By contrast, LTPoE++ solutions require only a single PSE and PD controller, result­ing in significant board space, cost and development time advantages.

LTPoE++ does not rely on the Link Layer Discovery Protocol (LLDP). LLDP is the IEEE-mandated PD software-level power negotiation scheme and requires exten­sions to standard Ethernet stacks, which can represent a significant software development effort. LTPoE++ PSEs and PDs autono­mously negotiate power level requirements and capabilities at the hardware level while remaining fully compatible with LLDP-based solutions. LTPoE++ gives designers the choice of whether to imple­ment LLDP, or not. This is useful for proprietary end-to-end systems that choose to forgo LLDP support. This eliminates ”power islands,” which reduces BOM costs, board size and complexity.

The LT4275 is a fourth generation PD controller and the first to offer very high power levels via LTPoE++. Most other PD controllers are compliant with either the PoE or PoE+ standard and provide less than 25.5W. Plus, the LT4275 is compatible with Linear Technology’s existing LTPoE++ PSE controllers: the 12-port LTC4270A/LTC4271 chipset, 8-port LTC4290A/LTC4271 chipset, 4-port LTC4266A and single-port LTC4274A. The LT4275 is the successor to the LTC4265 PoE+ PD, released in 2008.

Operating Modes

Fig. 2 shows the PD section associated with the LT4275. This circuit covers several operating modes depending on the input voltage sequence applied to the VPORT pin. These modes include 25kΩ signature detection, classification, mark, inrush and powered on.

During detection, the PSE looks for a 25kΩ signature resistor that identifies the device as a PD. The PSE applies two voltages in the 2.8V to 10V range and measures the corresponding currents. The PSE calculates the signature resistance using ΔV/ΔI measurement.

The LT4275 presents its precision, temperature-compensated 24.4k signature resistor between the VPORT and GND pins, allowing the PSE to recognize a PD is present and requesting power to be applied. The LT4275 signature resistor is smaller than 25kΩ, which compensates for the additional series resistance introduced by the IEEE required diode bridge.

The LT4275 recognizes a PSE as either Type 1 hardware complying with the IEEE 802.3af 13W power level, Type 2 hardware, complying with IEEE 802.3at 25.5W power level or LTPoE++ hardware complying with 38.7W to 90W power levels. For efficient power allocation, PD users can configure a classification that represents the PD power usage.

The detection/classification process varies depending on whether the PSE is Type 1, Type 2, or LTPoE++. A Type 2 PSE may use Type 1 classification signaling and later renegotiate a higher power classification with the PD over the data layer. PSE functions include:

  • Type 1 PSE, after a successful detection, may apply a classification probe voltage of 15.5V to 20.5V and measure current.
  • Type 2 PSE may declare the availability of high power by performing two-event (Physical Layer) classification or by communicating over the (Data Link Layer) high speed data line. A Type 2 PD must recognize both types of communication. Layer 2 communications take place directly between the PSE and the PD application, so the LT4275A/LT4275B responsibility ends with supporting two-event classification.

In two-event classification, a Type 2 PSE probes for power classification twice. The LT4275A or LT4275B recognizes this and pulls the T2P pin down to signal the load that Type 2 power is available. If an LT4275A senses an LTPoE++ PSE, it alternates between pulling T2P down and floating T2P.

LTPoE++ Classification

The LT4275A allows higher power allocation while maintaining backwards compatibility with existing PoE systems by extending the classification signaling of IEEE 802.3.

The RCLS resistor sets the classification load current corresponding to the PD power classification. Connect the RCLS resistor between the RCLASS pin and GND, or float the RCLASS pin if class 0 is required. The resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classification circuit.

Once the PSE detects and optionally classifies the PD, the PSE then powers the PD. The external MOSFET acts as a source follower and ramps the voltage up on the output bulk capacitor thereby determining the inrush current. To meet IEEE requirements, you should design inrush current to be approximately 100mA.

Surge Protection

A 100V absolute maximum rated input voltage means the LT4275 can survive and protect PDs from the most common Ethernet line surges. A programmable auxiliary power pin with signature corrupt provides support down to 9V. The LT4275 also includes a power good (PWRGD) output, onboard signature resistor, undervoltage lockout and comprehensive thermal protection.

The PWRGD pin is held low by its open drain output until HSGATE charges up to approximately 7V above HSSRC. The PWRGD pin holds off the isolated power supply until inrush is complete and the external MOSFET is fully enhanced. The PWRGD signal also simplifies the isolated power supply design, because it delays power supply startup until the CPORT capacitor is fully charged.

The LT4275 specifies an absolute maximum of 100V, however it will tolerate brief overvoltage events. Pins that interface to the outside world can routinely see excessive peak voltages. To protect the LT4275, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ58A between VPORT and GND. This TVS must be mounted near the LT4275.

The LT4275A/LT4275B/LT4275C DFN package has an exposed pad that is internally electrically connected to GND. The exposed pad may only be connected to GND on the printed circuit board.

Avoid excessive parasitic capacitance on the RCLASS pin and place resistor RCLS close to the LT4275. For the LT4275A, place RCLS++ nearby as well. For maximum protection, place the input capacitor (CPD) and transient voltage suppressor as close to the LT4275 as possible.

The IEEE 802.3 specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. During classification, however, the power dissipation in the LT4275 may be as high as 1.5W. The LT4275 can easily tolerate this power for the maximum IEEE timing but can overheat if this condition persists abnormally.

The LT4275 is thermally protected from overheating. If its junction temperature exceeds the overtemperature threshold, the LT4275 pulls down the HSGATE and PWRGD pins and disables classification.

The input diode bridge introduces a voltage drop that affects the voltage range for each mode of operation. The LT4275 can tolerate these voltage drops.

Connect a 0.1μF capacitor from VPORT to GND to meet an IEEE 802.3 input impedance requirement.

The LT4275 comes in industrial and automotive grades, rated for operating temperatures of -40°C to 85°C and -40°C to 125°C, respectively. It is available in RoHS-compliant 10-pin MSOP or 3mm x 3mm DFN packages.

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About the Author

Sam Davis

Sam Davis was the editor-in-chief of Power Electronics Technology magazine and website that is now part of Electronic Design. He has 18 years experience in electronic engineering design and management, six years in public relations and 25 years as a trade press editor. He holds a BSEE from Case-Western Reserve University, and did graduate work at the same school and UCLA. Sam was the editor for PCIM, the predecessor to Power Electronics Technology, from 1984 to 2004. His engineering experience includes circuit and system design for Litton Systems, Bunker-Ramo, Rocketdyne, and Clevite Corporation.. Design tasks included analog circuits, display systems, power supplies, underwater ordnance systems, and test systems. He also served as a program manager for a Litton Systems Navy program.

Sam is the author of Computer Data Displays, a book published by Prentice-Hall in the U.S. and Japan in 1969. He is also a recipient of the Jesse Neal Award for trade press editorial excellence, and has one patent for naval ship construction that simplifies electronic system integration.

You can also check out his Power Electronics blog

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