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We generally associate the Power Distribution Network (“PDN”) with the power circuits used to drive CPUs and FPGAs. The increasing use of FPGAs in our products certainly means that at some point we will all need to be fluent in PDN. In reality, PDN applies to all circuits and not just FPGAs and CPUs. Even everyday glue logic, such as high speed CMOS gates can wreak havoc in a PDN. The ultimate results of poor PDN design range from non-functional circuits in cases where the PDN fails to maintain adequate voltage regulation to the high speed circuit, to noisy circuits, where the PDN noise flows through the system through various distribution paths, such as PCB crosstalk or regulator PSRR. While understanding and optimization your PDN can require a great deal of effort, including expensive 3D simulations, the fundamental concepts can be simply stated in five key points.
Keep it flat
Most PDN books tell you that the best performing PDN impedance looks flat over frequency. That is because noise signals are generated as a result of discontinuities or impedance peaks in the PDN. The PDN is comprised of resistance, inductance and capacitance associated with the PCB traces and planes, the decoupling capacitors and their parasitics and the package parasitics including the bond wires and die capacitance of the high speed devices. Minimizing the Q of these resonant circuits is the key to obtaining a flat impedance. One of the fundamental PDN management tools is target impedance. This is the impedance below which all peaks should be maintained for good performance. The target impedance concept may have significant flaws [1], but it is still the most common PDN design technique in use today. However, the more basic goal should be to maintain the impedance as flat as possible up to a bandwidth that is dependent on the edge speed of the load signals, the amplitude of the dynamic current change and the impedance of the PDN. Note that this is the edge speed and not the pulse repetition frequency dependent.
Impedance matching is key
Test equipment manufacturers have understood this relationship for many decades. The use of a matched source and a matched load, connected through a matched cable is not an accident. The most common impedance in use is 50Ω though there are other less common impedances, such as 75 Ohms for TV applications. The reason for this is that the lowest PDN impedance occurs when the source and load impedances are exactly equal. Matching the interconnect impedance, the load impedance and the source impedance are really just another way of saying keep it flat, as any mismatch will result in either increased capacitance or inductance, either of which are undesirable.
Low rates have higher probability of issues
While it might appear that the higher the signal frequency, the more prominent the PDN issue might be, this is not always the case. The increased signal frequency certainly does carry with it an increase in signal integrity concerns, but not necessarily for the PDN. The reason that the lower frequencies are a bigger issue is simple. Looking at a low duty cycle pulse we will see every harmonic of the pulse frequency and with somewhat constant amplitude. For example, a 100kHz clock signal introduces signals with spectral content that are 100kHz apart. Increasing the pulse frequency to 1MHz results in spectral signals that are 1MHz apart. The likelihood of finding a PDN resonance very close in frequency to a spectral signal from the pulse is much greater with the lower frequency pulse rate. We can see this clearly using a 100kHz pulse and a 1MHz pulse as shown in Figure 1 and Figure 2.
Multiple issues are additive
Contrary to what many PDN books tell us, the noise voltage resulting from a dynamic current change is not limited to the product of the current step and the target impedance. It can be much larger. First, the fundamental FFT of the current signal is increased by a factor of 4/PI if the square wave current signal is applied at the PDN’s resonant frequency.
If the PDN has multiple resonances (peaks in the AC impedance), it is possible that several signals will be excited simultaneously and phase shifted allowing them to reinforce one another in the worst possible alignment[2].
Know your edges
One possible way to manage PDN noise is by selecting the slowest edge devices that suit your application. The maximum spectral frequency is associated with the rise and fall time of the current signal. Fast edges mean that the harmonics extend to higher frequencies, increasing the likelihood that the noise signal will find a resonance close by. Depending on the devices creating this signal, the speed can be as fast as 20pS in DDR3 memory circuits or in the case of a POL switching regulator, possibly as slow as 1nS. A high speed CMOS gate can reach a 10% to 90% rise time of 350pS and the 3dB frequency of the spectral content can then be estimated to be:
An edge rise time of 350pS therefore has a 3dB bandwidth of approximately 1GHz; falling at approximately 20dB/decade. As a general rule, the spectral content should be measured to a decade above fmax. This allows margin for high frequency resonances while there is still signal content. So for a high speed gate with a rise time of 350pS it is wise to measure the spectral content to 10GHz. An example of a CMOS gate is shown in Figure 3. With a rise time of 417pS the spectral content is well above 2GHz at the gate supply pins, so that you will want to use at least a 4GHz scope and preferably 20GS/s
While there is certainly a lot more to PDN than what is included here, this should provide some insight into why every engineer should be knowledgeable about PDN issues and how they affect circuit performance.
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