The process of correlating SPICE models to bench data often leads to discoveries of second-order and sometimes third-order parasitic elements that significantly impact circuit performance. A couple of these side effects — a reduced circuit “Q” and a circuit Q that is dependent on an IC's input power-supply voltage and output circuit loading — seem to be relatively common, or at least prevalent in several recently modeled ICs.
These Q variations result from an unforeseen output series resistance. These parasitic “resistors” are in series with the MOSFET and have several ramifications. The first is a reduction of the output filter Q, which generally results in improved phase margin. Using this additional phase margin may allow the designer to improve power-supply performance. If the designer is unaware of the Q reduction, the zero compensation generally will be placed at a lower frequency than necessary, which reduces optimum performance. Other aspects that may be affected would include the closed-loop parameters such as step-load response and line-transient response.
To create a SPICE model, it is customary to compare or “overlay” bench-test waveforms with simulation waveforms to see discrepancies clearly. This term for such an error first appeared during the comparison process for a low-voltage n-channel MOSFET, synchronous-buck-regulator controller where the measurement did not initially coincide with the simulation results.
Fortunately, the mathematics relating to the analysis of this phenomenon is relatively simple, so the root cause can be determined without too much difficulty.
As an example, we can use a simple forward-converter power stage. To isolate the particular effects we wish to evaluate, we took some liberties with the model's development:
The output diodes are ideal and have infinitely small resistance effects.
The output inductor is ideal with no series resistance.
The MOSFETs exhibit an ideal dc model, and gate-drain capacitance (CGD) and gate-source capacitance (CGS) are ideal linear capacitances.
The MOSFET on-resistance (RDSON) is its minimum on-resistance value.
The output capacitor has an ideal constant ESR. Without any ESR, the simulation would take an infinite time to settle. This is a good place to reduce the circuit Q so that it will settle without affecting the dc regulation we are evaluating.
Parasitic MOSFET Resistance
Using the SPICE model of a forward converter in Fig. 1, we can easily calculate the timing of MOSFET switching and determine how that switching affects the MOSFET's average output voltage. After determining the effect on output voltage, we can differentiate with respect to the output current to determine the effective resistance caused by switch timing. These values, some of which appear in Fig. 1, have been chosen to facilitate our analysis of the forward-converter power stage:
The gate resistance (RG) = 20 Ω, the converter output current (IOUT) = 1 A, the MOSFET input capacitance (CISS) = 3×10-9 F, the transformer primary turns (NP) = 1, the transformer secondary turns (NS) = 66, the MOSFET transconductance (KP) = 0.2 A/V2, the MOSFET gate-source threshold (VGSTH) = 3 V, the high end of MOSFET gate drive (VDRIVEHI) = 12 V, the input voltage (VIN) = 20 V, the switching frequency (FSW) = 2.5×105 Hz, the MOSFET drain current (ID) = IOUT×NS/NP A, and RDSON = 0.75 Ω.
The first delay, TD1 (in sec), from the rising edge of the driver to the on-state voltage of the MOSFET is:
The current then rises until the drain current is equal to the output current (in actuality, this is the output current minus half the peak-to-peak inductor current). This occurs at a gate voltage of:
VGSON = 5.569 V at ID = 0.66 A.
TDc is the time (in sec) it takes for the drain current to rise to the level required to raise the switch node:
At the time TDc+TDc, the switch node will switch to the on state of VIN:
TDc + TDc = 3.743 × 10-8 sec.
This can be simplified to a total TDON delay (in sec):
TDON = 3.743 × 10-8 sec.
The next time delay, TDc, occurs from the falling edge of the driver signal to the on-state gate voltage (VGSON).
The average voltage lost to the two edges is determined as:
TLOSS = 8.634 × 10-9 sec.
The SPICE simulation results in Fig. 2 show a change in voltage for a change in current, which equals resistance. The TLOSS value shows a net gain in the on time at the switch node and is in excellent agreement with the simplified SPICE model:
VLOSS = 0.028 V
However, looking at the effects with respect to the output current and evaluating the derivative with respect to ID results in:
ROUT = 0.084 Ω, which now shows a resistive term.
Now, introducing the MOSFET gate-drain charge (QGD) term and assuming that the Miller capacitance is constant: QGD = 10×10-9 no, while CGD = QGD/VIN = 5×10-10 F.
Next, the derivative of VOUT with respect to ID, which is a resistor, is taken by MathCAD:
ROUT = 0.131 Ω.
Note that the addition of the CGD term affected MOSFET timing and also significantly increased the magnitude of the output-resistance term.
Fig. 2 shows the relative timing of the signals and both the delay before the leading edge of the switch node and the delay of the turn off of the switch node are apparent. The net gain is positive, meaning that the duty cycle of the switch node is greater than the duty cycle of the gate-drive signal, resulting in a positive voltage offset to the output. However, the derivative shows that the resistive term causes the delay to decrease with current.
Next, the load step of the circuit in Fig. 1 is simulated and the output voltage and Q are measured. The results of the simulation will be used to verify the resistance, by evaluating the dc voltage change caused by the change in current.
The values are then compared with computations with and without the added parasitic resistance effect, as shown in Figs. 3, 4 and 5.
Next, we calculate ROUT in the same manner as before, except with different parameters in order to show that the parasitic resistance value can become fairly large. For the circuit in Fig. 1 and the following parameters: FSW = 8×105 Hz, VGSTH = 1.9 V, QGD = 0 no, VDRIVEHI = 8 V, RDSON(Q1) = 0.755 Ω, ESRC1 = 0.5 Ω, L1 = 100×10-6 H, C1 = 20×10-6 F, duty cycle = 0.4 and NT1 = 0.66 turns ratio.
The calculated ROUT is: 0.399 Ω. This is much greater than the 84 mΩ initially computed.
RSERIES is the total resistance including the ESR and the reflected RDSON. It also would include the inductor's DCR. It is the total resistance that affects the Q without the newly defined ROUT and is calculated as:
Q = 3.541.
Now, including the series calculated ROUT:
Q(0.084) = 3.125
Q(0.131) = 2.932
Q(0.399) = 2.17.
Fig. 4 is the average equivalent SPICE model, and Fig. 5 is a plot of the circuit's Q.
The mathematics behind the MOSFET switching characteristics clearly show there is a series output-resistance term that affects the circuit Q and the dc output voltage. This term cannot be used to calculate an equivalent power loss, since it does not constitute the entire switching loss, but rather the derivative of the switching loss with respect to the output current.
The mathematical and SPICE simulation results are in excellent agreement, so there is high confidence in the results.
The effects of this resistance term will be evident in the open-loop gain measurements, as well as in the small-signal and large-signal performance of the converter or regulator. The effects can invalidate the state-space average model's results, causing it to be inaccurate at some operating points and accurate at others. The sensitivities of the various terms can be determined by differentiating the ROUT term with respect to each parameter. This resistance is sensitive to the gate voltages and, therefore, also generally sensitive to the input voltage. We often see this effect as a reduction of circuit Q and as a function of input voltage and/or load current.
Evaluating this term in SPICE requires highly accurate models of the MOSFET's gate-drive circuit. Many of the vendor-supplied SPICE models found on the web do not have sufficient fidelity to correctly portray this effect. In addition, the model needs to be validated for each new MOSFET used as the interactions with the gate drive will likely be different.