Addressing Interposer and TSV Quality Challenges

Semiconductor manufacturers are adopting 2.5-D and 3-D technologies to increase the performance and density of their devices through the use of silicon interposers and through-silicon vias (TSVs). Such devices can provide smaller form factors and lower power consumption while offering benefits such as allowing manufacturers to combine heterogeneous technologies—processes optimized for mixed-signal, logic, and memory, for example—in one package.

But as semiconductor designers and manufacturers pursue such strategies, they will need tools ranging from ATE systems and probe stations to software to address several challenges:

• In the development and silicon bring-up stage, they will need to characterize the devices and determine how the 2.5-D and 3-D structures affect signal integrity with limited, if any, access to internal signals in the 3-D structures.

• They will need to understand the thermal characteristics of the TSVs and other structures.

• They will require known-good die (KGD).

• They will need to assure the integrity of the TSVs or interposers and that the assembled die perform properly together.

• They will need to determine what level of structural and functional test will be required during production test.

And as of now, few specific tools are dedicated to 3-D IC test. That’s not to say test equipment vendors aren’t addressing the issue. Advantest has not publicly announced a 3-D IC test strategy, but Gary Fleeman, director of business development, is well aware of the challenges. Outsourced semiconductor or assembly test (OSAT) is readying production lines, but what the real flows will look like and exactly where test points will be inserted remain very much in contention, Fleeman said.

Infinity Probe for RF MeasurementsCourtesy of Cascade Microtech

Cascade, imec Address 3-D test

Other organizations addressing the issues include Cascade Microtech and imec, which announced last March that they were partnering to address 3-D TSV probe solutions. In a recent interview, Cascade CTO Eric Strid said, “We are working with imec to demonstrate the capability to probe TSV pads with minimal probe marks so they still can be bonded reliably. This is a key requirement for semiconductor vendors to be able to supply KGD for cost-effective module assembly. Our joint paper at ITC-20111 shows imec’s analysis of pad marks with our new technology that we think is readily compatible with high-reliability bonding. The next step is to assemble the modules and perform reliability testing.”

Strid was asked about silicon bring-up and the need to characterize the devices and determine how the 2.5-D and 3-D structures affect signal integrity with limited, if any, access to internal signals in the 3-D structures. “3-D stacking will exacerbate paths to critical nodes,” he said. “There sometimes are opportunities to significantly mitigate the problems. Specifically, the JEDEC Wide I/O Standard connects all of the TSVs through all of the DRAM chips, and so if the stack has the microbumps available as an assembly, then the memory bus will be an ideal access point for signal integrity and timing analysis. If, on the other hand, the top chip is full thickness or encapsulated, the only way to access that bus is by deprocessing or lapping the stack.”

Thermal Issues Critical

Strid said thermal concerns will be critical: “Some of the issues include CTE mismatches near the TSVs and thermal hot spots in the stack. Design rules will require a keep-out area with no active devices around the TSV, and the [design] tools need to model the heat flow through TSV stacks since some DRAMs can’t tolerate the likely temperatures if they are stacked directly on a logic layer.”

The Cascade CTO described the proper application of structural and functional production test as a hot topic. “On one hand, KGD test coverage will drive very detailed testing,” Strid said. “On the other hand, probing and testing technologies must step up to the challenges of high pin-counts, low probing forces, and lower cost-per-pin. The production test environment may need to control mechanical or thermal stresses to emulate the chips’ ‘mission mode.’”

As for commercial solutions, Strid said, “Commercially available probe stations are nearly capable of meeting the challenges of probing TSVs but need some improvement in force control and X-Y-Z alignment accuracy and planarity. ATE systems will require pin-counts up to several tens of thousands of pins. Super fine-pitch probe cards and the interface to the ATE system are even more challenging.”

Specific products that Cascade will offer, Strid said, include probe cards for 3-D applications with array pitches to 40 µm, first for engineering, and then for production testing. Already, he said, the company has provided probe cards for engineering testing of 3-D footprints to 40-µm array pitch. The probe cards, he said, are addressing characterization of Wide I/O DRAM, chip stacks, or logic interfaces to those DRAMS.

As for challenges still needing to be addressed, Strid said, “First, there is a big debate regarding whether passive interposers will need to be tested or whether the yield will be so high they won’t warrant testing. Second, what is necessary to adequately test a die that is 50-µm thick with 100,000 microbumps? Third, how will you power up and test a die that only has 2-µm diameter pads?”

These challenges can all be solved, Strid said. “It is a question of economics. We are focusing on technologies that print probes so we can scale pin-counts within a given area cost effectively,” he concluded.

Testing TSV-Based I/O

The key challenges that Fleeman at Advantest sees include production test of TSV-based I/O. True TSV-I/O, such as that used on Wide I/O JEDEC memory, is limited in driver strength and can be susceptible to ESD, according to Freeman. “Many, many devices are going to come with TSVs, but most will have traditional I/O strengths,” he added.

Many customers, Fleeman pointed out, specify that test equipment “must not contact the TSV or micropillar grid array (MPGA)” because of concerns related to ESD as well as damage to the pad or pillar. More recently, he said, the ESD issue has abated; instead of no ESD protection there is some, “but it’s clear the handling systems and wafer handling must be capable of an almost zero ESD environment.”

The requirement for zero drive on the I/O, said Fleeman, would imply the use of an “unconventional test method, not existing ATE solutions.”

“For a known-good memory or known-good memory stack (KGS), we believe a production test solution for true TSV-I/O must include the capability to contact and test the I/O,” Freeman continued. He cited one foundry/OSAT as saying, “It is not KGD unless all the pins have been tested at spec.”

Fleeman concurs: “We believe the stacking of memory and resulting KGD and KGS requires full spec test,” assuring KGD and KGS after thinning and after stacking. He acknowledged that for SoC test, “many suppliers have had excellent yields without ever testing all the I/O at-spec. However, with stacking and thinned wafers, Advantest believes yield is the number 1 issue, and thus more coverage for KGD is required even for the SoC.”

As for interposers, Fleeman agreed with Strid at Cascade that there is a “huge concern in the industry over interposer yield.” However, Fleeman said, “Interposer suppliers plus tool providers like Applied Materials say the yield is virtually perfect” for the 65-nm three- or four-layer metal structures.

“Loss due to assembly or transport wouldn’t be caught in the interposer test anyway,” he continued. “For RDL [redistribution layer] and basic interposers, we don’t think there is a production [test] requirement. Line monitoring already is accomplished by very good picoamp DC testing and X-ray and optical inspection. Still, for development and initial characterization, an interposer test approach will be necessary.”

PXIe-4141 Source-Measure Units
Courtesy of National Instruments

The Partial Assembly Conundrum

Fleeman also addressed partial assembly. “This is the new world. You cannot put an $80 memory KGS on an interposer with a $20 SoC and have any yield loss at all,” he said. “We think there are opportunities for new ‘partial assembly steps’ to keep the final yield very high” although issues will remain related to thermal control, additional contacting steps (with additional opportunities for damage), and contact availability. “As stacks get more complex, even budget RF singulated devices better be KGD to protect the cost of yield loss.”

Fleeman concluded by saying, “Advantest supports continued improvement in coverage at KGD today, at the wafer level, with direct docking and further migration of final test quality and coverage to the wafer level. We believe in KGS for outstanding yields for consumer applications such as those involving Wide I/O memory stacks. And we believe in bare die KGD quality for SoC and memory, including some partial assembly insertions,” particularly for 2.5-D structures.

As 3-D test details evolve, organizations are offering resources that address the problems. SEMATECH, for example, provides a wiki and invites comments and inputs on topics related to TSVs for CMOS image sensors, high-volume manufacturing for Wide I/O DRAM utilizing TSV technology, and other topics related to 3-D integration.

Events Address 3-D Test

For its part, SEMI offered a forum for the industry to discuss materials, equipment, manufacturing, and product standardization as well as test at its SiP Global Summit held last September in Taiwan. SEMI reports that 25 industry executives shared their viewpoints on expediting time-to-market and reducing costs for 3-D IC production with about 1,060 attendees.

Specifically related to test, imec Scientific Director Eric Beyne said stand­ardization with respect to the extension of 2-D testing architectures will be key for effective 3-D testing. Amer Cassier, senior product engineer at Qualcomm, emphasized improving yield rates by implementing innovative KGD solutions. Roger Hwang, director of ASE Group, discussed collaboration across IC design houses, foundries, and testing houses. Sam Ko, deputy director of KYEC, said adherence to design for test (DFT) principles and a standard IC interface for each die stack would pave the way to reduced test cost.

Benjamin N. Eldridge, senior vice president, R&D and CTO of FormFactor, focused on the use of standard testing socket solutions to detect errors and bugs early in the process of wafer thinning and die stacking. And Greg Smith, general manager of the Semiconductor Test Division at Teradyne, described a towerless prober docking solution that could ensure signal accuracy and keep equipment cost down.2

An event dedicated to 3-D IC test was the second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, convened in conjunction with the 2011 International Test Conference. The list of sponsors for this event—Advantest, Cadence Design Systems, Intellitech, Mentor Graphics, Microprobe, Synopsys, Syntest, and Tokyo Electron—shows the interest test companies have in the topic as they pursue solutions.

As Dr. Phil Garrou puts it in his “Insights From Leading Edge” blog, over the last few years, primarily universities were involved in developing 3-D test protocols, but now “the 3-D-Test Workshop list of corporate sponsors says all we need to say” about the desire of major design and test houses to be involved.3

Organizers report that the 3-D-Test Workshop, as it’s known in short, focuses on test of and DFT for 3-D stacked ICs (3-D-SICs), including systems-in-package (SiP) and package-on-package (PoP) with an emphasis on 3-D-SICs based on TSVs.

Erik Jan Marinissen of imec and the founder and program chair of 3-D-Test Workshop reports in his “3-D InCites” blog4 that keynoter Hong Hao, vice president at Samsung Semiconductor, said the smart mobile device market has shown mind-boggling growth enabled by progress in 3-D packaging although several electrical and mechanical test challenges remain. And Jan Vardaman, president of TechSearch International, cited TSV wafer probing and testing as unresolved equipment challenges.

Cadence, Mentor Graphics, Synopsys, and SynTest presented DFT approaches for 3-D SICs. Cadence and Mentor focused on die wrappers as proposed in the IEEE 3-D-Test Working Group (3-DT-WG) P1838 Standard that allows for the transport of test data up and down through the die stack.

With respect to wafer probing, Marinissen reports in his blog that Ben Eldridge, CTO of FormFactor, described the company’s NanoPierce metal nanofiber contacts. And Matthew Losey of Touchdown Technologies discussed a multilayer MEMS probe card at a 40-µm pitch.

Finally, Marinissen notes, manufacturers had their say, with representatives of austriamicrosystems, ST Microelectronics, and TSMC commenting on defects observed in TSVs. The next 3-D-Test Workshop is slated for Nov. 8-9 at the Disney Hotel in Anaheim, CA.

BGA Socket for High-Speed Probing Stacked Memory and Processor Courtesy of Ironwood Electronics

3-D Test Products

Despite the dearth of dedicated 3-D IC test products, companies are developing or already offering solutions, often based on existing product lines. Strid of Cascade said, “Our microwave probes such as the ACP and Infinity Probe® Series are regularly used for interconnect characterization, which will be needed as TSVs are used at higher frequencies, especially in mixed-technology modules. We also offer probe systems that can be configured to support probing of 3-D ICs for engineering development.”

 GOEPEL electronic has added features in its TAPChecker™ EDA Software for the generation of BSDL test benches. The newly developed options extend the software’s flexibility in terms of handling pin groups and complex port declarations for improved coverage of multichip modules and 3-D chips. Users now are able to assign special vector sequences to complete port groups or adopt complex bus structures into the simulation. Ironwood Electronics recently introduced a series of BGA sockets for high-speed probing of stacked memory chips and processors to support debugging of 3-D devices during the design phase, making signals available to an oscilloscope or logic analyzer.

In addition, Joey Tun, senior product manager for precision DC measurements at National Instruments, said NI PXIe-4141 Source-Measure Units (SMUs) are suitable for 3-D IC test applications because of the high channel density, 10-pA current resolution, and four-quadrant (source-sink) capability. Tun explained that the instrument can be used at various stages of the 3-D IC fabrication process, ranging from pre-bond wafer test to wafer test and final testing. The list of tests the PXIe-4141 can perform includes KGD verification with I-V parametric test and bonding resistance measurements (on C4 bumps and TSVs).

In addition, he said, NI SourceAdapt technology featured on PXIe-4141 allows test engineers to customize the output response of the SMU to compensate for highly capacitive contacts (in depleted or inverted regions) to attain stable measurements with minimum transient times while preventing accidental overshoots that can damage the DUT.

No doubt test vendors will be continuing to apply existing products and technologies to test emerging 3-D ICs as they develop new solutions. And there is no doubt that 3-D chips are on the way.

At the RTI 3-D Architectures for Semiconductor Integration and Packaging Conference last December, CEA-LETI and ST-Ericsson described the development of a three-die stack with Wide I/O memory and logic. The successful tape-out of the device resulted from collaboration between these two organizations and Cadence Design Systems, which provided the design tools and the Wide I/O controller IP for the project.5 Such successes will spur on test vendors to redouble their efforts. And as Strid of Cascade put it, the challenges can be met—it’s now a matter of economics.


1. Smith, K., et al., “Evaluation of TSV and Micro-Bump Probing for Wide I/O Testing,” Proceedings of the International Test Conference, 2011.

2. “3-D-IC: Ushering in a New Era in the Semiconductor Industry,” SEMI, November 8, 2011,

3. Garrou, P., “IFTLE 72: 2011 IEEE 3-D Test Workshop,” ELECTROIQ, Oct. 23, 2011,

4. Marinissen, E.J., “3-D-TEST 2011 Workshop,” 3-D InCites, Oct. 13, 2011,

5. Goering, R., “Three Die Stack—A Big Step ‘Up’ for 3-D-ICs with TSVs,” Industry Insights, Cadence Design Systems, Dec.13, 2011.

For More Information

• 3D-IC Alliance: standards, literature, and events

• IEEE Computer Society Test Technology Technical Council: 3-D-Test Working Group

• IEEE Computer Society Test Technology Technical Council: 3-D-Test Workshop

• IEEE Standards Association: P1838 Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

• JEDEC: 3-D IC standards, including Wide I/O memory

• RTI International: 3-D architectures for semiconductor integration and packaging

• SEMATECH: 3-D interconnect wiki

• SEMI: SiP Global Summit

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