In the real world, end-user devices and services are driven by the ceaseless demand for instant access to more data in less time. This paradigm is no different for test and measurement where solutions have to move and analyze even more data in even less time.
This is one of the driving forces behind the increasing use of an integrated ecosystem of measurement modules, embedded processing modules, and space-efficient chassis. With the extensions built on PC-based technologies such as PCI Express (PCIe), PXI has emerged as the leading modular standard. A focus on data movement and the sharing of data among integrated modules and systems is one of the major differences between PXI and typical box instruments.
Stepping Back and Looking Back
To better understand data movement in PXI, let’s look at the underlying protocols. PXI originally was based on the 32-bit PCI standard, which uses a parallel link providing 133 MB/s of bandwidth shared among the connected peripherals. To keep pace with the demand for higher throughput, the standard evolved with 64-bit buses and faster clocks.
This led to PCIe, which builds on PCI’s software and interface structure to allow complete backward compatibility with PCI host systems and the associated software. The main difference is in the physical implementation: PCIe uses point-to-point communications based on differential signaling technology and high-speed serial data. It also moves away from PCI’s bridging scheme to use a switching technique that presents each peripheral with its own link.
Of course, PCIe isn’t strictly serial. The dedicated bandwidth to any peripheral can be scaled through the use of multiple parallel lanes per link. By using PCIe switches that allow multiple simultaneous point-to-point connections, systems with an efficient switching topology can create massive parallelism and consequently even greater data bandwidth.
Taking a Few Steps Forward—Sort of
All these advantages are beginning to benefit measurement devices in the form of PXIe. The roots of this standard go back to the adoption of Compact PCIe—the ruggedized form of PCIe—as the foundation of PXIe.
Hardware compatibility is another matter. Because there were so many existing products in the older PXI-1 format, PXIe architects had to ensure compatibility—but this led to trade-offs and compromises in some instances. Ultimately, hybrid slots capable of supporting both the 32-bit PCI and PCIe protocols seemed like the best approach.
However, the notion of using all hybrid-compatible slots forced chassis designers to confront two harsh realities: highly complex signal routing and the circuitry space required for the various connectors and supporting ICs in an all-hybrid system. As a result, most of today’s PXIe chassis contain an inflexible mix of PCI, hybrid, and first-generation PCIe-only slots. This limits where users can place different types of cards and, in some cases, could handcuff test-system designers.
Further compounding this challenge, some systems divide slots into segments controlled by their own switch. In such cases, peer-to-peer communications between modules often are limited to just the segment (four slots) unless the host controller contains a second-level switch to switch between the segments. However, this architecture further increases latency. Finally, another limitation comes from currently available PXI infrastructures that restrict lane counts to peripherals.
Moving to the Next Level
A new breed of chassis provides fast, all-hybrid slots and an open infrastructure. Modules have up to 4 GB/s of available bandwidth, and controllers have up to 8 GB/s of system bandwidth.
In addition, by architecting a sophisticated switching topology, an entire system can be configured as a single peer-to-peer segment in which capable devices can communicate with each other directly without host intervention. By providing all-hybrid slots, either PXI or PXIe modules can be placed in any position. With the improved switching topology, peer-to-peer and controller-to-module communications speeds are optimized.
With a new-found focus on how data moves within a system, PXIe architects have delivered the highest bandwidth, lowest latency standard platform for module-to-module and module-to-system data sharing. The result is measurement solutions that move and process more data in less time—and the ultimate result is more capable test systems.