ChipVORX Technology Extended to Altera Arria V FPGAs
September 3, 2012. GOEPEL electronic has announced the availability of the first ChipVORX model libraries for the new generation of Arria V GX FPGA devices from Altera. ChipVORX supports embedded test and embedded programming.
ChipVORX provides users the opportunity to implement embedded system access (ESA), omitting nail or probe contacting. With this latest version, under JTAG control the Altera FPGAs are utilized as natural, design-integrated test centers, helping to increase test quality and to reduce effort.
“Especially the integrated transceivers’ low power consumption has been an important feature for a number of customers on the field of communication solutions to use the new Arria V FPGA in their future designs,” said Heiko Ehrenberg, technology officer for ESA with GOEPEL electronic. “Our new ChipVORX models simultaneously provide ideal support applying innovative test and programming strategies. The ChipVORX technology’s reusability plays a particular role throughout the entire product life cycle. The FPGA embedded instruments can be utilized for prototype verification as well as production test, debugging and fault diagnosis.”
The ChipVORX models are intellectual property (IP) for the implementation and control of chip embedded instruments. They enable several FPGA-assisted test and programming functions, including test of time-critical DDR-SDRAM, programming of parallel NOR and NAND flash devices, frequency measurement, and high-speed programming of serial boot flash.
Within the ChipVORX framework instruments are temporarily loaded, configured, and finally controlled as soft macros via the standard IEEE 1149.1 TAP into the FPGA. The entire work flow is fully automatic and synthesis-free. For all test, measurement, and programming procedures there are automatic generators that also analyze the UUT’s functional structure and establish an interconnection from instrument to signal pin (IP to pin). Furthermore, the opportunity of interactive graphical control panels facilitates debugging.
The ChipVORX models for Arria V FPGA were developed in cooperation with GATE alliance partner Testonica. The usage of the ChipVORX requires neither expert background knowledge nor specific FPGA tools or continuous IP adjustments. The execution of ChipVORX-based routines is possible on each run-time station without further options. Also Gang applications can be implemented.
The Arria V ChipVORX IP models are supported as standard starting from SYSTEM CASCON version 4.6.1 and are activated by the licence manager like the system software. Regarding the hardware, ChipVORX is supported by the controllers of the SCANBOOSTER family, as well as by the SCANFLEX hardware platform.
Read a related article about ChipVORX.