Design for Test Tools Address Stacked Dies
The emergence of 3-D ICs presents test challenges that extend from design-for-test tools from design-automation companies to device handlers from equipment firms including Advantest and Multitest. A previous article covered handler issues from the perspective of Advantest and Multitest.1 A recent interview with Stephen Pateras, product marketing director for Mentor Graphics silicon test products, adds the design-automation perspective.
Pateras said, “We have been talking about 3-D test for a year and a half or more, and we see it as a growing requirement. We now have customers who are actually actively using some of our capabilities in relation to 3-D test.”
Stacked IC configurations come in multiple flavors, Pateras said, including 2.5-D and true 3-D, where you have vertically stacked dies interconnected using TSVs. Further, you’ll find differences depending on what you are stacking—you may be talking about stacking homogenous parts or heterogeneous parts.
“What we are seeing more right now is on the homogeneous side—in particular, memories stacked on memories which themselves then are placed on an interposer along side of one or more SoCs,” Pateras said, “And increasingly they will be placed on top of an SoC.”
“When you look at the 3-D problem, there really are two things the customer is concerned about,” Pateras continued. “One is yield of the stack that you are creating, and the second relates to then testing the stack itself as a whole.” The yield of the stack, he said, is related to how good the devices are that you are stacking together. “It comes down to how well are you testing the bare dies before you stack them? How good is your wafer-sort test?”
Historically, Pateras said, wafer-sort test tended to be less stringent and less comprehensive than final test or package test. That’s because of the difficulties in probing at wafer test, the high cost of fixturing, and the difficulties in applying at-speed test at wafer probe.
“People have just tended to do less of a test at wafer,” making wafer test more like a screening process,” he said. Then there would be some additional fallout that would be caught at package test.” The economics of the process, Pateras explained, made it less costly to permit some escapes at wafer test and catch the remaining bad devices at final test.
“But with 3-D,” Pateras said, “the economics change quite drastically because no longer are you throwing away one bad die in a package at final test. Now you are throwing away a stack of devices, many of which may be good, as well as probably a much more expensive package. So there now is the realization that as you are doing your 3-D stacking you need to start doing better wafer-sort test.”
Of course, the cost and difficulty of fixturing and probing at wafer test are not lessening, so, Pateras said, “We are seeing growing interest in more advanced test solutions at the wafer level, and these tend to include things like more low-access types of test.” He said he sees more interest in applying ATPG compression patterns at wafer-sort test to ensure known-good die (KGD) where comprehensive compression patterns can be applied without extensive I/O access at the wafer-probe level. “We are also seeing greater adoption of BIST,” he said, another low-access test method that generally requires only a JTAG test access port (TAP) interface to access the device under test.
Wafer Test Issues
In addition, he said, “Customers are looking to do improved I/O test at wafer, which historically was not something that people dealt with.” He said Mentor offers contactless I/O testing as well as leakage test and delay test on the I/Os by leveraging the boundary-scan chain and some other technologies that Mentor can implement on chip. “And that’s gaining a lot of traction in the 3-D space,” he said.
Pateras also explained that he is seeing growing interest in testing high-speed SerDes I/O in the 3-D space using BIST. In addition, he said, customers are leveraging Mentor’s relatively new Cell-Aware ATPG solution, which employs transistor-level fault models to target some internal defects. That technology, he said, is finding use in package test in automotive and medical applications as well as to enable greater quality test at the wafer level.
Producing KGDs at the wafer level is only part of the problem. “The second half of the problem,” said Pateras, “is, once you do stack your devices, how do you test the stack?” The process involves testing stacked DRAM or stacked logic dies or some combination plus the interconnections between them, be they interposers or TSVs.
DRAM Test Challenges
One challenge, Pateras said, is accessing each die in a stack. “We already have some customers doing stacked DRAMs that are placed on an interposer alongside an SoC, but whether the DRAMs are stacked on an interposer or directly on an SoC, the memory test problem is very similar.” The problem, he said, is that you need somehow to get access to all those memories for test.
Memory test tends to follow JEDEC standards, with tests applied, for example, in accordance with the JEDEC Wide I/O interface standard. If the devices follow the JEDEC standards, they will have a test interface built in.
“We support using that,” Pateras said, “although we prefer, and so far customers have adopted, a much more comprehensive approach, which is based on BIST. You can’t place BIST on bare memory dies themselves, but you can place BIST on the SoC,” whether it be directly stacked with the DRAM or placed on an interposer. “You put BIST on the SoC, and it communicates to the stacked DRAM dies though the functional bus. On the DRAM side, you need just add the BIST onto the SoC and let that BIST talk to the bus and test all the DRAM.”
Testing the Logic
To test multiple logic dies, Pateras said, you need access to each die—and whatever test resources reside within them—individually. “The problem,” he said, “is that in most cases when you stack devices in a 3-D configuration there are no outside connections to the stack except for maybe the bottom die. The other dies are only connected to each other—their immediate neighbors—with TSVs, so then how do you access them?”
One thing that’s being developed is a methodology for using the TSVs themselves for test access, which may involve reserving certain TSVs as test interfaces that can provide daisy-chain access through the stack to all of the various dies.
The IEEE P1838 Working Group is developing a standard architecture for such daisy-chain access to dies within a stack. As noted on the P1838 website, “The proposed standard defines die-level features, that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in pre-packaging, post-packaging, and board-level situations.”2
Of course, standards take time to develop and are not formalized in time to meet the needs of emerging markets. Consequently, said Pateras, Mentor had already developed its own proprietary approach, “…which is hopefully as close as we can get to what the standard ultimately will be.” Mentor’s approach, he said, involves reusing the JTAG TAP interface and includes additional control and muxing to allow daisy-chaining to local TAPs within the vertical configuration. The approach, he said, establishes a mechanism that can gain access to any of the dies in the stack.
“Once you have access to the various dies, you then need to be able to send and receive test data to each die,” Pateras said, adding that that’s where BIST also comes into play although scan-compression patterns can be applied as well. “Once we can access each die and potentially apply test to them, we need to test the TSV connections between those dies,” he continued. “What we’ve developed there is basically an interconnect test solution where we take advantage of boundary-scan cells on the I/Os. We add basically the equivalent of boundary-scan cells to the TSVs and then are able to use those cells to apply tests from one die to the next through those TSV connections. We create an optimal set of patterns that only targets the TSV connections between the dies.”
Adapting PCB Test Techniques
Pateras’ comments on 3-D IC test echoed, in part, remarks from Al Crouch, chief technologist for core instrumentation at ASSET InterTech, when he spoke at the Test Vision 2020 workshop held in conjunction with Semicon West last July.3 A 3-D stack can look like a group of hard cores in a package amenable to traditional IC test techniques such as those based on stuck-at and delay-fault models, he said, and to support tests, stacks will require new access functions, including skip, bypass or pass-through, turnaround, on-die, and next die—reminiscent of the daisy-chaining Pateras referred to. These functions, Crouch said, will act as elevators, controlling up-down traffic. IEEE 1149.1 boundary-scan technology will play a key role in stacked-die test.
But Crouch said that, to him, a 3-D die stack looks like a PCB. With dies arriving from multiple sources, he said, problems can occur with respect to the die stacking order, die top-to-bottom orientation, die front-to-back orientation, and even the number of dies in a stack. When the dies are stacked into a final packaged cube, he said, the cube will need to be verified, and power and thermal issues will need to be addressed. Consequently, he said, 3-D structures might be amenable to PCB-based test techniques based on PCOLA (presence, correctness, orientation, live, alignment), SOQ (shorts, opens, quality), and FAM (features, at-speed, measurement) test techniques.
Tools Available Now
The test challenges surrounding 3-D structures will only become more difficult as the structures themselves become more complex. The emergence of such devices will require sophisticated products that span the gamut from design automation tools to test systems and handlers.
In addition to the Advantest and Multitest handlers, some of the tools already are in place, including Mentor Graphics’ Tessent for 3D-IC Test. The Tessent silicon test and yield analysis tools address KGD testing challenges by supporting ATPG, compression, logic BIST, memory BIST, boundary-scan, mixed-signal BIST, and silicon learning. The Tessent tools also support test of stacked memory-on-logic and logic-on-logic.
From an ATE perspective, some equipment that can handle 3-D test is in place as well. Speaking at Semicon West in July, Scott Chesnut, a senior ATE applications engineer at Advantest, cited the applicability of the V93000 Test System to handle 3-D IC test chores.4 3-D IC structures require test at the chip level and then the stack level, he said, and the same test program should be used for each to reduce the correlation burden.
He noted that the SmarTest Program Manager for the V93000 can handle such tasks. Furthermore, he said that the Advantest Concurrent Test Framework can cut the test time and improve test coverage. In addition, he said, the V93000’s clock-domain-per-pin and protocol-engine-per-pin features can serve 3-D IC test applications, and he said the system can perform precision parametric testing for TSVs and interposers.
The Future of 3-D
Illustrative of where 3-D devices might be headed is the e-CUBES initiative, a European effort to develop fully integrated, high-TSV-count devices that include radios, application layers, and energy harvesting and storage capabilities. The e-CUBES can serve health and fitness, aeronautics and space, and automotive applications. As such devices come to fruition, test products will evolve to keep pace.
References
1. Nelson, R., “Vendors Drive IC Advancements,” EE-Evaluation Engineering, September 2012.
2. P1838—Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits, IEEE Standards Association.
3. Nelson, R., “Malefactors Expected to Attack 3-D ICs,” EE-Evaluation Engineering Online, July 14, 2012.
4. Chesnut, S., and Smith, R.J., “ATE Solutions to 3DIC Test Challenges,” Test TechXPOT Presentation, Semicon West, July 10, 2012.