3-D IC test workshop caps ITC activities

Anaheim, CA. A workshop on 3-D IC test capped Test Week activities held in conjunction with the International Test Conference. Workshop general chair Yervant Zorian, of Synopsys, welcomed attendees Thursday afternoon by noting that this year's event marks the third iteration, completing a two-year period in which 3-D technology has emerged from the conceptual stage toward maturity with researchers achieving realistic results. He noted that the 3-D concept is not new—we have long had MCMs and SiPs—but what is new is the use of through-silicon vias (TSV) to communicate from layer-to-layer among stacked dies.

Ivo Bolsens, VP and CTO at Xilinx, delivered a keynote address titled “The Evolution of 3-D ICs: The Road to Production of a 6.8B-Transistor FPGA.” He noted that FPGAs have been successful in riding the tide of Moore's law but that the industry now faces opportunities and choices that might not be clear-cut. “Doubt is not an agreeable condition,” he quoted, “but certainty is absurd.”

But doubt, though inevitable, should not impede progress. Bolsens cautioned attendees not to believe everything they read on the Internet. Rumor once had it, he said, that Moore's law would run into a power wall—chips would simply get too hot. But that problem was solved with multicore architectures. Similarly, a seemingly inevitable design technology gap was closed by EDA companies' development of reusable IP. He noted that Xillinx has been working on 3-D technology since 2005 and brought a product to market in 2011. “3-D was for us seen as essential,” he said.

Following Bolsens, Paul Franzon of NCSU presented an invited address titled “3-D-Driven System Design—Present and Future.” He noted that TSVs have become a manufacturing reality, enabling the development of image sensors, memory cubes, stacked FPGAs, and memory-on-logic devices. Further development, he said, will lead to “extreme 3-D” with heterogeneous integration.

Franzon said that both cost and power considerations will affect 3-D IC penetration into mobile devices. The question, he said, is, what can you do with 2 W? He noted that a DDR3 interface requires 4.8 nJ per word, while a TSV can require only 2 pJ per word. With 3-D, he said, “Data motion is no longer expensive.”

A panel session titled “The 3-D Buzz: Hype vs. Reality” was one of the highlights of the Friday workshop sessions. Panel participants included Françoise von Trapp, founder/director of 3DInCites; Ira Feldman, principal consultant at Feldman Engineering Corp.; Herb Reiter, president of eda2asic; Jan Vardaman, CEO of TechSearch International Inc.; and consultant Paul Werbaneth.

Under the guidance of von Trapp, who served as moderator, panelists described the Gartner hype cycle: it begins with a technology trigger, overshoots to a peak of inflated expectations, and descends to a trough of disillusionment. If the trough of disillusionment doesn't turn into a valley of death, the cycle continues through a slope of enlightenment and on to a plateau of productivity.

If there was a consensus among panelists and audience as to where 3-D technology sits on the curve, it seems to be near the transition from the trough of disillusionment to the slope of enlightenment. Werbaneth said the trough did not turn into the valley of death, and Vardaman noted that the fact that test issues are being addressed is a strong signal that the technology is moving up the slope of enlightenment.

One question is, who will lead in 3-D adoption? Reiter said he sees the need for 3-D devices in computing and networking to achieve needed bandwidth and latency performance. But Feldman questioned whether risk-averse data-center personnel would quickly adopt the technology. Conversely, mobile device manufacturers may hesitate to adopt 3-D chips because of the cost of the technology. Then there is the question of obtaining the necessary capital. Werbaneth said venture capitalists would rather invest $100M in many social-networking startups than a single physical built-out.

Nevertheless, the consensus seemed to be that the technology is moving forward, despite investment and technological challenges. “Reality has set in, and we have work to do,” said von Trapp, adding, “but we need to make this happen. We can't reach the functionality we need without it.”

Complementing the panel and addresses at the one-and-a-half-day workshop were paper and poster sessions focusing on making the technology happen. Topics included 3-D design for test, 3-D wafer probing, 3-D electronic design automation, 3-D cost modeling and yield issues, and 3-D test quality and yield analysis.

Of particular note was a Friday morning address describing work by ST-Ericsson and Leti to investigate TSVs and their impact on DFT. Stephane Lecomte of ST-E noted that testability challenges relate to pre-bond TSV coverage and stacking DFT, adding that there is an ongoing DFT standardization effort under the auspices of IEEE P1838. 3-D integration, he said, presents new defect types, requiring that pre-bond TSV patrametric coverage be available at an acceptable cost. He concluded that 3-D DFT should allow post-bond parallel test execution between die to provide post-bond test-time reduction. Key takeaways, he said, are that TST prebond coverage is reqired, 3-D DFT must rely on extending 2-D DFT techniques, and 3-D DFT must enable reuse at the test-program level. 3-D TSV integration is an improving technology, and 3-D DFT must improve as well, he concluded.

For more information visit http://3dtest.tttc-events.org/