Panel sessions, corporate presentations; sessions on topics such as jitter and phase noise, new-generation ATE, board and system test, and scan compression; and a chip maker's commentary on the coming IJTAG revolution were all highlights of the International Test Conference, with Test Week concluding Thursday afternoon and all day Friday with workshops on such topics as 3-D IC test. Here is a day-by-day summary of some key activities.
Monday November 5
Panel 1: Entrepreneurship in Test CEO
A Monday evening panel convened executives Benny Madsen of LitePoint, Mark Roos of Roos Instruments, Gayn Erickson of Aehr Test Systems, Bill Bottoms of 3MTS, and Dan Glotter of OptimalTest. Each member was asked to speak about a pre-arranged position relating to the session title. Bill Bottoms spoke first, basing his comments on his earlier experience as a venture capitalist rather than as 3MTS CEO.
Bill Bottoms: In general, he thought that the ATE business wasn’t very attractive as it stood. However, if a company developed an innovative approach—a paradigm shift—then it could be.
Regardless of the business involved, the largest opportunities existed at technical inflection points, and VCs looked to invest at those times. In addition to the proper timing, it was important that the company founders had already invested their own money before VCs would risk theirs.
Finally, Bottoms cited some of the more recent trends that might contribute to a paradigm shift. Embedding the necessary test resources in the chip isn’t a new idea, but neither is it being done on a scale that removes the need for external ATE. If it were, Bottoms noted a couple of advantages such as shifting the hardware cost to the fab and providing the capability to perform continuous testing while running in mission mode.
Mark Roos: Roos described his desire to “do his own thing” as the motivation behind forming Roos Instruments in 1989. Previously, he had worked on microwave instrumentation at HP, leaving to join EIP Microwave as VP of engineering. Although this was an interesting and important job, Roos said that while at HP he realized he needed to understand how a company actually worked before starting his own. His time at EIP was part of the process.
Roos Instruments received a small business innovative research (SBIR) grant via DARPA, which allowed development of a software-centric measurement system. This minimal hardware approach is a feature of Roos microwave ATE systems.
Gayn Erickson: Now CEO, president, and director at Aehr Test Systems, Erickson previously held various executive positions at Verigy and Agilent Technologies. Erickson spoke about the relationship among cost of test, technical challenges associated with shrinking geometries, and demands for ever-higher reliability.
Although his comments involved his earlier experience, they were very directly based on Aehr Test activities. He said that stacked die were becoming more common, necessitating the use of known-good-die (KGD). This, in turn, required burn-in and test, capabilities Aehr Test had developed for full wafers. Especially for stacks with more than two chips, using KGD afforded much lower costs than test after packaging.
Different levels of reliability were needed for consumer products such as cell phones, compared to a much higher level for devices embedded in cars. Erickson thought these levels only could be guaranteed after extensive burn-in regardless of the design and manufacturing processes. In addition to functional test, small geometry devices have to be monitored for power supply current to sort chips according to their leakage current.
Dan Glotter: With both semiconductor test and financial management experience, Glotter provided wide-ranging comments. In common with some of the other panel members, he stressed the need to be flexible and to continually ask yourself, what can you do better? You can’t be so wedded to one idea that you fail to quickly and sometimes significantly adapt if that approach fails. For example, Roos stated that he had to reverse course after his first design.
Glotter said that he concentrated on production data flow as the key to improving quality and reducing cost: test data is a gold mine of information. Finally, he said VCs wouldn’t invest in hardware alone—there needed to be something truly different that the company was doing. In his case, Glotter obtained funding from Israeli VCs.
Benny Madsen: Now part of Teradyne, LitePoint was founded in 2000 to further wireless communications. Initially, the company provided design consulting, which led to development of an in-house tester. Rather than being general purpose, the tester returned precise parametric measurements that otherwise were difficult to obtain. Soon, the company started “following the chip sets,” creating specialized test sets to meet new standards and address more complex test requirements.
A factor in common with Roos Instruments was LitePoint’s self-funding approach. Madsen said that self-funding supported the need to change direction as you understand the market better. Also, he said that self-funding helped him establish the culture necessary to double business every year.
Tuesday November 6
Two Presentations in the Corporate Forum Series
Goepel: Three approaches were listed by which test access could be gained: embedded system access (ESA), intrusive board access (IBA), and native connector access (NCA). Of these, both NCA and IBA were claimed to lack diagnostic information. ESA, by contrast, is based on JTAG access and can feature processor emulation and P1687-style embedded instruments.
Goepel has based its solutions on the single System Cascon software platform.
R&D Circuits: This presentation dealt with the low-level effects that determine loadboard high-speed performance. The company’s products address two types of applications: device characterization and continuing production.
Loadboard development begins with the PCB material itself, which can vary in thickness and composition. Especially for continuing production that requires all loadboards to have identical characteristics, the company sorts material batches to get the best match.
At high speeds, through vias create significant reflections, so they are back-drilled to minimize the effect. Nevertheless, because of machining and material tolerances, some small stub remains that is compensated by adding a tuning section. Among other technologies, the company offers coaxial vias and can develop loadboards with from 30 to 64 layers.
Session 2: Jitter and Phase Noise
1) Dr. Ding from Altera discussed timing variation in 28-nm designs running at 28 Gbps. He cited layout-dependent effects and the lack of appropriate test equipment. In part, the test problem follows from the lack of accessibility to internal nodes, for which he said that on-die instrumentation was required.
2) Allan Ecker, a graduate student at The University of Washington, described a digital method for phase-noise measurement. The approach was based on a precise time-to-digital converter. Ecker discussed a simulated case study in detail. However, in response to a question from the audience, he confirmed that the proposed method relied on at least 12 bits of resolution and 1-ps timing accuracy. This combination was thought to be impractical by high-speed circuit experts also in the audience.
3) Xian Wang from Georgia Tech presented a method of interleaving high-speed DACs with their outputs offset 90° from each other. The approach appears to have a sound theoretical basis although no hardware exists at this point. Prof. Gordon Roberts, in the audience, suggested that the design was similar in effect to performing a Hilbert Transform followed by mixing.
Session 4: New-Generation ATE for New-Generation Challenges
1) A paper by a group of Advantest authors described bi-directional pin electronics. One of the objectives was to develop multipath current sources that could be switched to create pre-emphasis. The example of a telephone hybrid circuit was used to explain the principle. The circuit developed to accomplish the directional switching used both differential and common mode effects. If the circuit is driven differentially, the midpoint of a resistive divider between the complementary outputs remains at a constant level. However, if only one side is driven by the return signal, the midpoint follows that signal.
2) D. C. Keezer from Georgia Institute of Technology described a multi-GHz arbitrary timing generator. In contrast to many other papers that were entirely based on simulations, Prof. Keezer’s work had been extended to an actual working prototype constructed from commercially available parts.
The design is based on an eight-phase 400-MHz clock. Each of the phases drives a programmable delay and the outputs from the delay elements are exclusively ORed to generate the final 3.2-Gb/s rate. Although the whole design is innovative, what stands out is the use of an FPGA and extensive algorithms to figure out which delay elements should have what delay, and to program all eight of them at full speed. A 10-ps resolution was demonstrated with complete control of the pulse pattern. In addition, two eight-phase generators were interleaved to obtain 6.4-Gb/s output speed.
Wednesday November 7
Session 9: Scan Compression
1) A paper jointly prepared by authors from Synopsys and NVIDIA proposed separating scan chains with lots of X states from those without. The immediate benefit is that for the chains with no X states, there is no ambiguity in the MISR result. A separate circuit deals with the chains having X states.
2) N. Mukherjee from Mentor Graphics, one of the developers of the company’s TestKompress product, described a low-power programmable PRPG. The aim was to reduce toggling to keep the power low, but also to run the necessary patterns. This design features deterministic control of a phase shifter to increase the number of “care bits” in the patterns. Although the quantity of necessary patterns increases as the toggling is reduced, the technique allows the user to control the relationship and therefore meet a power target if that is the main criterion.
Mentor Graphics Luncheon Presentation: The Coming IJTAG Revolution
Joseph Sawicki, vice president and general manager of the Mentor Graphics Design-to-Silicon Division, presented the company’s Tessent IJTAG tool. It provides automation support for the IEEE P1687 standard—not yet voted upon. Jeff Rearick, a senior fellow at AMD and editor for the IEEE P1687 working group, discussed the proposed standard in detail. Stefan Eichenberger, DIX technology manager, commented on implementation of P1687 and its relationship to IEEE 1149.1.
In P1687, a procedural description language (PDL) describes how the individual instruments are used. An instrument connectivity language (ICL) describes the instrumentation interfaces and connections among them. The Tessent tool automatically extracts ICL code at any level of the hierarchy. In addition, PDL commands written in isolation can be applied to a new level within the P1687 hierarchy.
Actual P1687 approval may not occur in the short term. During Rearick’s presentation, the comment was made that P1687 actually extends to a great deal of detail. Nevertheless, the working group members appear to be in agreement on the basic features, and those features are being supported in a number of proprietary products such as Tessent IJTAG.
Session 13: Board and System-Level Test
1) Agilent’s Ken Parker discussed capacitive testing of modern memory devices. The basic problem is that the sensed capacitance is extremely small—only a few femtofarads. The solution Parker proposed involves building the devices with a larger metallic surface either directly as part of the chip or added to the packaging. He said that there was room to do this in modern devices and that the result was at least a 3X increase in capacitance, corresponding to a much larger difference between a chip being present and being absent.
2) A. Jutman from the Tallinn Institute of Technology reviewed the use of IEEE 1149.1 and P1687 in the context of FPGA-based synthetic instrumentation for board test. December 5, 2012 is the deadline for 1149.1 ratification.
3) Zoe Conway from Cisco Systems presented research conducted into board assisted BIST. This was a very high level discussion that centered on the relationship between IC BIST and board test. What tools available as IC BIST would be most helpful if they could be deployed during board test rather than only for testing the IC on which they were resident?
Panel 3: Managing Process Variation in Analog Designs
Panel members were A. Frisch of Intel, D. O’Riordan of Cadence Design Systems, G. Roberts of McGill University, S. Sunter of Mentor Graphics, and M. Tirupattur of Analog Bits
Each panel member presented an opening position with perhaps most of the value of the session occurring in the later exchanges. Roberts discussed built-in self calibration (BISC), which centers a design within the process variation. This type of approach differs from calibration at manufacture because BISC accounts for aging.
Sunter expanded on the idea, commenting that modern designs can have a large number of self-adjusting loops—similar to a radio’s AGC. Formal analog fault simulation is needed to ensure test coverage. He suggested more automation was needed and the question of whether to test open- or closed-loop also was important. With regard to on-chip test circuitry and its additional cost, Sunter offered a rule of thumb that equated one tester-second to 1E6 gates in a 22-nm process.
M. Tirupattur focused on the need for physics-based design to improve reliability. This would take the form of better circuit architectures and layouts. He specifically referred to the large amount of heat generated by multi-core processors.
Thursday November 8
3D-Test Workshop
The workshop opening session included several paper presentations after introductory remarks by the General Chair, Yervant Zorian.
1) Ivo Bolsens from Xilinx discussed the technology developed to support production of a 6.8-Bn transistor FPGA. Key is the use of several smaller IC slices and their interconnection by a multilayer silicon interposer having many thousand thru-silicon vias (TSV).
2) Prof. Paul Franzon from North Carolina State University presented several examples of 3D system design. In particular, the high speed and low power advantages of TSVs were clearly evident. The work was sponsored by a number of companies and several of the projects included both a design/simulation phase as well as actual fabrication. When asked about the performance of the devices, Franzon said it wasn’t very good, in part because at least one of the processes was poorly characterized.
3) A paper jointly written by authors from Mentor Graphics and The Chinese Academy of Sciences describing the application of JTAG to a memory/logic stack connected by TSVs was well received. JESD229, the JEDEC 3D boundary scan specification, was referenced. Two additional instructions were needed to deal with the TSV test control registers and to provide total access to all parts of the design.
4) Brandon Noia, a PhD student from Duke University, discussed the stress-induced change in mobility caused by the difference between copper and silicon thermal coefficients of expansion. To account for this effect, Noia proposed design library modifications to account for a device’s location relative to a TSV. Although the research to date only dealt with residual stress remaining from manufacturing, sufficient design margins must be provided to allow correct operation over the chip stack’s operating temperature range.
The workshop continued on Friday. See related post.
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