The “Special Report—Test Applications” in our January issue focuses on the software tools as well as logic analyzers, protocol analyzers, BERTs, phase-noise testers, spectrum analyzers, vector network analyzers, and oscilloscopes that you can use for high-speed serial bus characterization, debug, and test. You can read that article here.
In this “Web Exclusive” companion article to the January print special report, industry experts elaborate on pre-emphasis, software tools, and the signal-integrity challenge. Scroll to the end of this article for links to additional resources.
Hiroshi Goto, business development manager at Anritsu, described pre-emphasis as one of the most effective techniques to open the closed eye on high-speed backplanes and interconnects, such as Infiniband 26G-IB-EDR and 32G Fiber Channel. “The basic concept of emphasis technology is to give higher amplitude to the bits before and after the transit from zero to one or one to zero to compensate for the loss of the transmission path at the higher frequencies,” he said.
Theoretically, Goto said, emphasis technology could completely compensate for the loss and phase delay given an implementation with an unlimited number of taps. “Such a solution in the real world, however, is very expensive and complex,” he said.
He explained that a more efficient and practical way for opening a 28 Gbit/s eye is 4-tap emphasis with one-bit tap setting resolution. The amplitude of each tap can be adjusted independently up to 20 dB. For 10 Gbps and below, a one post cursor is acceptable, he said, but for 28 Gbps at least four taps are required for the error-free data transmission when data goes through 30-inch PCB.
Goto said the 4-tap emphasis approach can be used in conjunction with a BERT to simplify and shorten the emphasis setting procedure and to help reduce measurement and design verification times by automatically finding the ideal emphasis settings based on the reverse characteristics of the DUT. He added that aa vector network analyzer (VNA), such as Anritsu’s VectorStar, can measure the loss and phase delay versus frequency characteristics to find the best setting of 4-tap emphasis during simulation. The VNA can acquire the DUT's s21 parameter data, which is inverted and added to the input signal as emphasis settings.
Chris Loberg, senior technical marketing manager at Tektronix, provided an overview of software capabilities that can assist in serial bus testing. For advanced serial bus analysis, he said, Tektronix offers a set of analysis tools that can be applied across multiple serial bus standards to conduct a deeper level of analysis beyond compliance testing.
DPOJET jitter and timing analysis software, he said, runs on DSA70000 Series Oscilloscopes and separates jitter into components for further debugging of root cause of timing errors. He described DPOJET as the analysis engine behind many standards-specific timing measurement requirements. He added that both the DSA8300 Sampling Oscilloscope (Option 80SJNB) and the BERTScope (Option JMAP) provide jitter separation, including critical NP-BUJ, and eye-diagram analysis results.
“As serial bus speeds increase, margin becomes increasingly scarce and analysis is needed to understand how the effects of fixtures, cables, and connectors impact margin performance,” Loberg said. To support this need, Tektronix offers Serial Data Network and Serial Data Link Analysis tools (SDNA & SDLA, respectively), which provide insight into margin performance by characterizing fixture effects and removing those effects from the measurement path. In addition, he said, SDLA can account for changes to measurement results through the addition of equalization efforts (DFE and FFE, for example) that open up closed eye diagrams.
For serial bus standards-specific analysis, he said, Tektronix provides DPOJET-based options with standards-specific eye masks and predefined instrument setups to ensure consistent measurements that can be compared with industry standards. For standards that are in a very early adopter stage, he said, Tektronix recently added an Application Developer’s Toolkit to its DSA70000 Series Oscilloscopes to enable engineering teams to setup their own automation framework in DPOJET. This capability, he said, is popular for development teams working on proprietary serial buses—such as ones used in the government military research field.
Tektronix also offers a serial-bus test-automation framework, Loberg said, which can help engineers streamline complicated test procedures defined by serial-bus standards organizations. Called TekExpress, it includes a seamless link into deeper analysis tools like DPOJET. TekExpress automates the setup, execution, and reporting of select serial-bus standards tests, which in some cases involve more than 100 tests and multiple equipment setups. TekExpress controls the operation of Tektronix pattern generators (AWGs and BERTScopes), oscilloscopes (DSA70000 and DSA8300 Series), RF switches, and customer DUTs.
In addition, Loberg said, Tektronix offers serial bus debug and analysis tools that enable Tektronix instruments to provide fingertip access to debugging capabilities. He described Pinpoint Trigger System on the Tektronix DSA70000 Series Oscilloscopes as a comprehensive triggering system designed to capture over 1,000 different types of trigger conditions, including serial patterns and logic thresholds. Complementing this trigger system, he said, is the newly announced Visual Trigger, which simplifies complex triggering by providing an area-based approach to setting a trigger condition. “Visual Trigger lets the debugging engineer define the complexity of the trigger condition by drawing it on the scope’s display.” Loberg said.
Another debugging tool is Serial Bus Decoding, which is available on DSA70000 Series Oscilloscopes. Serial Bus Decode options, he said, translate incoming waveforms back to bits, which can be re-constructed into hexadecimal and/or protocol-based bus traffic on the scope’s display. A number of these tools are unique to a serial bus standard. For proprietary serial bus decoding, Tektronix provides a Customer-Defined Serial Bus option.
For serial bus receiver testing, Loberg said, the BERTScope provides in-depth analysis tools, including a unique Error Location Analysis option, which provides the precise bit-error location on a capture PRBS pattern, allowing the debugging engineer to backtrack to the probable cause of an inflated BER number. In summary, Loberg said, “When compliance testing fails, Tektronix provides answers to keep serial bus design efforts moving forward.”
The Signal Integrity Challenge
Avoiding signal integrity problems has become a key part of the design engineer’s job, according to Ken Johnson, director of marketing for oscilloscopes; Dr. Alan Blankman, product marketing manager for signal integrity; and David Li, product marketing manager—all at Teledyne LeCroy. The signal-integrity challenge, they said, stems from the advent of the “post-PC era”—in which smart phones, tablet PCs, and cloud computing have helped to drive the development of multi-lane serial data communication standards, such as PCIeGen3 and 40/100 GbE. As bit rates increase to 28 Gbps per lane, they said, design engineers require “…high-speed, high-fidelity oscilloscopes that can acquire and analyze multi-lane differential signals to understand signal-integrity issues that cause crosstalk and inter-symbol interference and that lead to closed eyes and bit errors.” Also, they said, engineers need “…affordable network analyzers that are easier to use and more rugged than a traditional VNA in order to measure S-parameters to use in simulations and to verify models.” In addition, they said, engineers need bit error rate testers that are protocol-aware for receiver tolerance testing, and they need protocol analyzers test adherence to the protocol requirements of serial data standards.
Teledyne LeCroy, they said, offers a complete toolkit for high-speed serial-data transmit, receive, and serial-data-link characterization, including oscilloscopes, bit error rate testers, network analyzers, and analysis software. The tools support complete serial data and crosstalk analysis to perform thorough debug and analysis on gigabit-speed signals. The company offers toolsets for multi-lane serial data and crosstalk analysis and synchronized protocol analysis and physical-layer capture.
At the core, they said, is the signal acquisition technology embodied in the company's oscilloscopes, which offer bandwidths to 65 GHz, serial data trigger capability to 14.1 Gbps, and up to 80 synchronized channels using the company's ChannelSync architecture. In addition, the company's SDAIII-CompleteLinQ software allows engineers to find and understand the root causes of closed eye diagrams, timing jitter, vertical noise, and crosstalk on up to four differential lanes, simultaneously.
Agilent Technologies Resources:
- “High Speed Digital Videos,”
- “Digital Design & Interconnect Standards,”
- “Achieve signal integrity in high speed design,”
- “PCIe 2.0/3.0, PCI Express Design & Test Information Resource Center,”
- “PCI Express Transmitter Electrical Validation and Compliance Testing with Agilent Infiniium Oscilloscopes” (Application Note),
- “How to Pass Receiver Test According to PCI Express 3.0 CEM Specification with Add-In Cards and Motherboards” (Application Note), and
- “Crossing the Digital-Analog Divide” (White Paper).
- “Overcoming High-Speed Interconnect Challenges” (White Paper),
- “Signal Integrity—Frequency Range Matters!” (White Paper),
- “Signal Integrity Analysis of 28 Gbit/s High-Speed Digital Signal” (Application Note), and
- “Ideal Pre-Emphasis Constant Setting” (Application Note).
Rohde & Schwarz Resources:
- “Analysis of Jitter with the R&S FSUP Signal Source Analyzer” (Application Note),
- “Phase Noise Measurement up to 50 GHz with High Dynamic Range” (Application Note), and
- “Optimum PLL settings for Phase Noise Measurements with the R&S FSUP” (Application Note).
- “Triggering Fundamentals Primer,”
- “Debug Timing Issues with DPOJET, the Core Analysis Engine,”
- “DDR Verification Techniques,”
- “Debugging using 8b10b Decoding,”
- “Debugging with DPOJET,”
- “Debugging with Visual Trigger,”
- “Thunderbolt Compliance Testing,” and
- “Choosing the right platform for Jitter Measurements.”
- Tektronix Technology Support Pages:
Teledyne LeCroy Resources:
- “Understanding SDAIII Jitter Calculation Methods” (White Paper),
- “Configuring Properties of Time Domain Traces in SPARQ and SI Studio” (Technical Brief),
- “ChannelSync” (Technical Brief),
- “Mode-Multiplexed 6 x20-GBd QPSK Transmission over 1200-km DGD-Compensated Few-Mode Fiber” (Technical Paper Presented at ECOC), and
- “Space-Division Multiplexed Transmission over 4200-km 3-Core Microstructured Fiber” (Technical Paper Presented at ECOC).
View previous online exclusives:
“'We don't judge, we measure',” and