MIT's p-type transistor offers improved carrier mobility

Researchers at the MIT's Microsystems Technology Laboratories (MTL) have developed a germanium p-type transistor whose carrier mobility doubles that of previous experimental p-type transistors and which nearly quadruples that of commercial devices.

The MIT News Office announced January 3 that MTL researchers presented the device at the December IEDM.

Judy Hoyt, a professor of electrical engineering and computer science at MTL, reported that the transistor's improved hole mobility results from straining the germanium—compressing the germanium atoms by growing them on top of different layers of silicon and an SiGe composite.

The MIT News Office quoted Hoyt as saying, “It’s kind of a unique set of material structures that we had to do, and that was actually fabricated here, in the MTL. That’s what enables us to explore these materials at the limits. You can’t buy them at this point.” Added graduate student James T. Teherani, “These high-strain layers want to break. We’re particularly successful at growing these high-strain layers and keeping them strained without defects.”

The researchers also reported that the transistor uses a trigate design in which the gate wraps around three sides of a raised channel. The MIT News Office quoted Krishna Saraswat, the Rickey/Nielsen Professor in Engineering at Stanford University, who was not involved in this research, as saying, “The germanium part helps in increasing the drive current, and the trigate part helps in reducing the leakage in the off state. So a combination of those two just gives you an ideal transistor for the next generation.”

MIT Technology Review described a trigate transistor in a May 6, 2011, article.


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