Introspect Technology Addresses Engineering Gap with Compact SerDes Instrument
January 27, 2013. Introspect Technology, a provider of compact and embedded high-speed digital instrumentation, has announced the SV1C Personalized SerDes Tester to address a gap in high-speed digital-product engineering tools.
The company (formerly DFT Microsystems) describes the SV1C Personalized SerDes Tester as an ultraportable, high-performance instrument that creates a new category of tool for high-speed digital product engineering teams. It integrates multiple technologies in order to enable the self-contained test and measurement of complex SerDes interfaces such as PCI Express Gen 3, DisplayPort, Thunderbolt, or MIPI M-PHY. Coupled with a seamless, easy-to-use development environment, this tool enables product engineers with varying skill sets to efficiently work with and develop SerDes verification algorithms. The SV1C fits in one hand and contains eight independent stimulus generation ports, eight independent capture and measurement ports, and various clocking, synchronization, and lane-expansion capabilities. It has been designed specifically to address the growing need of a parallel, system-oriented test methodology while offering signal-integrity features such as jitter injection and jitter measurement.
With a small form factor, an extensive signal-integrity feature set, and a software development environment, the SV1C is suitable for signal-integrity verification engineers that perform traditional characterization tasks as well as FPGA developers and software developers who need rapid-turnaround signal-verification tools or hardware-software interoperability confirmation tools. Product engineers can now spend their valuable time innovating on their interface control algorithms, addressing urgent debug challenges, or performing automated data collection tasks using their own personalized test sets. The SV1C integrates all the commonly needed functions such as digital data capture, bit-error-rate measurement, clock recovery, jitter decomposition, and jitter generation.
Designed for users with widely varying backgrounds and expertise, SV1C’s ESP Software environment provides PC-based interaction with the hardware, thus accelerating debug tasks, while simultaneously offering automation capability. The ESP software makes the SV1C system suitable for engineers who want to seamlessly develop tests, debug devices, and verify high-speed physical-layer (PHY) protocols in engineering, production, and failure analysis.
The SV1C Personalized SerDes Tester features multiple DUT control and communication interfaces such as JTAG, I2C, and SPI, thus allowing engineers to seamlessly interact with their DUT’s internal registers from within a single development environment consolidating test and setup into one interface.