Semicon West Participants Offer Updates on EUV, 3-D Transistors, and 450-mm Manufacturing

April 25, 2013. The critical processes and technologies necessary to continue Moore’s Law are currently more uncertain than ever before in the history of advanced semiconductor manufacturing, according to SEMI. To assess these uncertainties and provide the latest information on EUV lithography, 3-D transistors, 450-mm wafer processing, and other challenges to preserving the pace of Moore’s Law, the leading authorities on these critical issues will provide their insights, perspectives, and predictions at Semicon West, July 9-11, in San Francisco.

Novel Transistor Architectures

The mobile market is driving the move to novel transistor architectures that offer greater performance and power benefits than traditional planar architectures. Memory and logic manufacturers are pursuing different strategies including leveraging innovations in design rules, new channel materials and processes (e.g., MOCVD), and inspection and metrology challenges. Semicon West speakers and topics on the challenges of nonplanar transistor processing include

Joe Sawicki, Mentor Graphics, “New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology”;
Gary Patton, Ph.D., IBM Semiconductor Research and Development Center, “Meeting the Challenges of Next-Generation Scaling”;
Subramani Kengeri, GlobalFoundries, “Enabling SoC Level Differentiation Through Advanced Technology R&D”;
Michel Haond, STMicroelectronics, “Main Features and Benefits of 14-nm Ultra Thin Body and BOX (UTBB) Fully Depleted SOI (FD-SOI) Technology”;
Paul Kirsch, Ph.D., SEMATECH, “Non-Silicon R&D Challenges and Opportunities”; and
Adam Brand, Applied Materials, “Precision Materials to Meet FinFET Scaling Challenges Beyond 14 nm.”

Progress in Lithography

Although progress to take EUV lithography into the realm of high-volume manufacturing continues to be made, the readiness of source technologies, mask infrastructure, and resist performance are still not known with a high degree of certainty. Until EUV lithography is ready for high- volume manufacturing, the industry will continue to rely on double-patterning and even multiple-patterning lithography schemes using 193-nm immersion technology to take it beyond 22 nm. How the industry will address these barriers, uncertainties and alternatives will be the focus the lithography session at Semicon West, which will include the following speakers and topics:

Skip Miller, ASML, “NXE Platform Performance and Volume Introduction”;
Stefan Wurm, Ph.D., SEMATECH, “Mask and Resist Infrastructure Gaps”;
Ben Rathsack, Tokyo Electron, “Advances in Directed Self-Assembly Integration and Manufacturability on 300-mm Wafers”;
Mike Rieger, Synopsys, “Collaboration to Deliver Lithography Solutions”; and
Nikon Precision (presenter to be announced), “ArF Lithography Extension Through Advanced Overlay and Imaging Solutions.”

While materials, architecture, and processing technologies are undergoing revolutionary change, wafer processing platforms are also being radically transformed with a planned transition to 450-mm wafers. For chip manufacturers and suppliers, this will involve increased levels of collaboration, further advancements in tool prototypes, and increased visibility into related supply-chain implications. The SEMICON West 450 Transition Forum will provide the latest updates on the status of 450 R&D, as well as a review of key technology considerations and a discussion of implications and opportunities for the supply chain.

Each of these programs will take place in the TechXPOT conference sessions on the exhibit floor. Other TechXPOT programs include sessions on 2.5-D and 3-D IC packaging, productivity innovation at Existing 200-mm/300-mm fabs, silicon photonics, lab-to-fab solutions, MEMS, LED manufacturing, and printed and flexible electronics. SEMICON West will feature over 50 hours of free technical, applications, and business programs.

Free registration for Semicon West 2013 ends on May 10.

www.semiconwest.org/registration

See related article, “Big Data Comes to Semiconductor Test,” by Tom Morrow, vice president, SEMI.