IEEE 1149.1-2013 aims to slash costs through test reuse

IEEE today announced IEEE 1149.1-2013 “Standard for Test Access Port and Boundary-Scan Architecture,” which aims to cut costs by means of test reuse from IP to the system level. CJ Clark, Intellitech CEO and chairman of the IEEE 1149.1-2013 working group, said the updated standard provides a standardized plug-and-play interface for both mission IP (CPUs, DSPs, memory, analog, and connectivity, for example) and infrastructure IP (embedded test, BIST, and process monitoring, for example).

Although the original 1149.1 standard is associated with the terms “JTAG” and “boundary scan,” Clark cautioned that the term “boundary scan” has been a misnomer. With the new release, he said, standardization is now available for all internal JTAG registers via the TAP (Test Access Port). The 2013 version of the standard provides for hierarchical descriptions of on-chip IP and a hierarchical on-chip operational language for on-chip IP. In addition, it offers synergy with IEEE 1500 (“Standard Testability Method for Embedded Core-based Integrated Circuits”) and IEEE 1801 (“Standard for Design and Verification of Low Power Integrated Circuits”) to support reuse of IEEE 1500 structures and to support cross-power domains.

The new revision continues the original 1149.1 standard's functionality of testing interconnections between ICs assembled on a printed-circuit board. In addition, 1149.1-2013 now supports test of the IC itself and observation and modification of circuit activity during normal operation. All of the functionality can be accessed though the TAP.

Clark said the boundary-scan TAP constitutes a foundation that enables test of a chip in-circuit and that can be of use across the supply chain. Traditionally, he said, “The IP provider has his purpose and mission, and the IC designer has her purpose and mission.” The new standard enables a knowledge-transfer technique that spans the IP provider, IC designer, the system OEM, and the board test engineer. The new standard eliminates the need for proprietary languages at each stage along the supply chain, resulting in significant labor cost savings.

The IEEE notes that 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on Tcl—and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers. Eight new optional IC instructions provide a foundation for configuring I/Os for board test, mitigating false failures when re-testing the IC at the board level and correlating the results back to wafer-level test through an Electronic Chip ID (ECID).

Clark emphasized that the new standard can support ecosystem tests, in which it helps system integrators evaluate the interactions of ICs with supporting PCB components. The new standard, he said, supports not only IP designers but also IC designers, OSAT engineers, PCB designers, and test engineers. He noted that semiconductor ATE provides a perfect environment—a chip that functions well in that environment might not function properly in the real world. The ECID provides a way to correlate real-world performance with ATE test results.

As the IEEE puts it, “The revision of IEEE 1149.1, the first for the standard since 2001, allows critical domain expertise for intellectual property (IP)—how to configure a serializer/deserializer (SERDES) for loopback testing, for example—to be transferred in a computer-readable format from the IP designer to IC designers and, in turn, to designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain. The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars.”

Clark noted that there is a place for creativity, but that place is not in creating “anything goes” DFT. “Cost savings occur when interfaces are familiar, consistent, repeatable, and don't require new training or analysis,” he said.

Clark said the standard—400 some pages in length compared with 200 for the original version—represents more than two years of effort on the part of 25 working-group members meeting twice per week.

IEEE 1149.1-2013 is available for purchase at the IEEE Standards Store.

See related article, “Intellitech Supports Silicon Instruments through IEEE 1149.1-2013 Standard.”


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