September 12, 2013. JTAG Technologies BV showcased several JTAG Live products as well as new systems upgrades at this years’ International Test Conference in Anaheim.
With JTAGLive CoreCommander, engineers can now activate the OCD (on-chip debug) modes of a range of popular cores to affect kernel-centric testing. While many devices are now equipped with JTAG (IEEE 1149.1) boundary-scan registers (BSRs), which are used extensively to provide test access into digital and mixed-signal designs, a significant number of microprocessors and DSPs can be found with deficient or even nonexistent boundary-scan test registers. For the electronics test engineer this can, at best, be frustrating as they look to employ alternative methods for testing the processor and/or associated cluster/peripheral components.
CoreCommander routines are suitable for diagnosing faults on dead-kernel boards in either design debug or repair, since no onboard code is required to set memory reads and writes. Boundary-scan deficient parts can also be better utilized during production test, as CoreCommander-driven functions increase fault coverage. Since CoreCommander is Python-based it complements perfectly the JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronized testing to full boundary-scan devices.
The solutions take control of key processor core functions using the built-in emulation/debug functions of the processor core and are designed by test engineers for use by test engineers. JTAG CoreCommander uses dual modes of operation, namely Interactive or Python embedded.
CoreCommander for FPGAs is a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port (TAP) to proprietary IP cores (for example, DDR controllers, E-net MAC, and USB controllers) and harness them for test purposes.
The base of CoreCommander for FPGAs is a RTL (Register Transfer Language) coded translator block that provides access to proprietary IP cores through commonly implemented bus structures such as Wishbone, AMBA, Avalon, and CoreConnect. This translator block can either be permanently or temporarily programmed into a gate array. Linker software provided with the module automatically links the translator block with IP blocks and the FPGA specific interface layer to build the complete file set that may be programmed in the FPGA. Access to the translator is subsequently provided by a Python (JFT) library module.
JTAG Live Studio is the company's latest package of JTAG/boundary-scan tools that enable designers and manufacturing test engineers alike to develop complete test and programming applications.
The benefits offered by the JTAG Technology for debugging, testing and in-system programming are not limited to complex designs with many JTAG devices. Designs with only a few, even just one or two, JTAG devices can also benefit from this technology during all stages of the life cycle. A toolset capable of handling even the most complex boundary-scan designs, however, often is not economically feasible for a company that only uses a few JTAG devices in its designs.
JTAG Live Studio establishes a new class of test and device-programming tool-set that dramatically lowers the cost of entry for test and hardware engineers. Alongside the many traditional benefits of JTAG/boundary-scan JTAG Live Studio gives access to newer technologies like processor-controlled test. Python-embedded mode uses a similar structure to that featured in the JTAGLive Script product, allowing CoreCommander functions to be embedded into Python code to create re-usable test modules for specific tests.
JTAG Live is the economical easy-to-use family of board debug tools from JTAG Technologies. Products within the family include Buzz, AutoBuzz, Clip, and Script.