GOEPEL debuts test and programming strategies for Bay Trail processors

Jan. 24, 2015

GOEPEL electronic has announced the development of specific model libraries for the testing and programming of Intel Bay Trail processors, which are part of the Intel Atom family. The libraries of VarioTAP models allow flexible execution of processor emulation tests using the native debug port. Users are now able to use the processor as an instrument for hardware design validation of prototypes as well as programming of flash devices.

Intel Bay Trail is a series of multicore SoCs based on the Silvermont architecture. Manufactured in a 22-nm process, the chips offer optimized performance with low energy consumption. Main application fields of the Bay Trail processors are mobile applications such as tablets and notebooks, but also hybrid and embedded devices. There are various Intel Bay Trail series with up to four processor cores and clock speeds up to 2 GHz.

The processors are integrated in µFCBGA (micro flip chip ball grid array) packages with several hundred pins and are mounted directly on the board, not allowing direct contact with external instruments. VarioTAP offers embedded instruments for test, hardware debugging, flash programming, and design validation even after mounting.

VarioTAP is a technology for processor emulation developed by GOEPEL electronic. Thereby, a processor is reconfigured to provide design-integrated test and programming instruments via the native debug port. A respective VarioTAP model, as part of an extensive IP library, contains all relevant access information for the respective target processor. On this basis users can select a processor corresponding to their design and be able to test and validate the connected hardware unit as well as program Flash memories.


About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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