ADLINK introduces 4-channel 12-bit 80-MS/s PCIe digitizer

May 13, 2015

ADLINK Technology Inc., a provider of cloud-based services, intelligent gateways, and embedded building blocks for edge devices that enable the Internet of Things (IoT), today announced the release of its new high-speed PCI Express digitizer, the PCIe-9814. It features four simultaneously sampled 80-MS/s input channels with 12-bit resolution, 40-MHz bandwidth, and up to 1 GB DDR3 onboard memory. The PCIe-9814 delivers compellingly accurate high dynamic performance in 76 dB SFDR, 64 dB SNR, and -75 dB THD, with up to 640-MB/s data streaming and value added functionality, enhanced price/performance, and maximum optimization for radar testing, power management monitoring, and nondestructive testing.

The PCIe-9814’s 80-MS/s sampling and 40-MHz signal bandwidth meet the requirements of medium frequency radar signal reception from IF radar receivers. The PCIe-9814 provides external digital trigger input for synchronous trigger radar signaling, while three extra synchronous digital inputs receive radar synch pulse signals or GPS IRIG-B code to support radar signal markers or synchronous time stamping used in radar testing.

The PCIe-9814’s FPGA-based 31-order FIR digital filter supports noise reduction when signal content is 20 MHz or less. Noise effects are reduced efficiently and signal visibility increased by rejecting out-of-band and background noise and unexcepted high-frequency signals, all with no extra programming demands. The FPGA-based FIR digital filter performs much faster than on the host, with no host CPU bandwidth occupied.

The PCIe-9814 supports Windows 8 and Windows 7 operating systems and is compatible with third-party software such as NI LabVIEW and Visual Studio.NET. In addition, ADLINK’s measurement APIs allow easy conversion of basic voltage/time measurement results with no need for extra programming.

http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=1524

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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