Research organizations CEA-Leti and imec recently have reported significant semiconductor-technology innovations with respect to silicon (Si) as well as materials beyond silicon. The reports aligned with last year’s International Electron Device Meeting (IEDM 2015) held Dec. 7-9 in Washington, D.C. Organizers describe IEDM as a forum for reporting breakthroughs in the areas of semiconductor and electronic device design, manufacturing, physics, and modeling—touching on devices ranging from CMOS transistors to sensors.
CEA-Leti presented new details about its R&D efforts in post-7-nm CMOS device architectures, materials, and computing-system paradigms at IEDM.
“Our tradition is to take a broad, production-oriented approach to technology development to reduce risks and accelerate the transition into high-volume manufacturing, and this is our approach for the post-7-nm realm,” said Olivier Faynot, manager of Leti’s Microelectronic Section, in the run-up to the meeting. “Our interdisciplinary exploration and analysis of upstream factors, like neuromorphic computing, give us a strategic perspective on device-level requirements, which in turn helps us evaluate options for new materials, transistor designs, and integration techniques.”
Emphasizing power efficiency
At a LetiDay event on Dec. 6, the organization shared details on ultra-low-power atomic-scale devices, emphasizing that power efficiency will be the key issue in post-7-nm generations expected to enter production in 2019. Leti strategic marketing manager Carlo Reita noted during a LetiDays event in Grenoble in June that nonrecurring engineering costs will reach $1.34 billion at the 5-nm node (totaling $2.24 billion with yield ramp-up costs added in), underscoring the need for more efficient design and implementation measures.1
Faynot expects to meet the challenges with new-generation CMOS logic, likely utilizing stacked nanowires, and resistive RAM memory technology integrated using 3D approaches. In October at the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference in Rohnert Park, CA, Leti researcher Sylvain Barraud demonstrated a viable integration path for stacked nanowires. In addition, benchmark studies show that stacked nanowires offer the best trade-off in terms of performance and parasitic capacitances, the key for energy efficiency.
Leti said it has about 20 scientists and engineers engaged in post-7-nm development plus an additional 10 researchers from partners, including IBM, STMicroelectronics, and academic labs.
In addition, Leti and its research partner CEA-Inac announced they are investigating a silicon-on-insulator (SOI) technology for quantum computing with proven scalability. In this approach, quantum dots are created beneath the gates of field-effect transistors, which are designed to operate in the “few-electron” (n-type) or “few-hole” (p-type) regime at cryogenic temperatures (below 0.1 K). The approach offers an alternative to semiconductor spin qubits realized in III-V materials, which have a limited lifetime because of coupling between the electron spin and the nuclear spins of the III-V elements.
Also, Leti announced it has developed two techniques to induce local strain in fully depleted (FD)-SOI processes for next-generation circuits that will produce more speed at the same, or lower, power consumption and improve performance. The first relies on strain transfer from a relaxed SiGe layer on top of SOI film. In a recent paper in the ECS Journal of Solid State Science and Technology,2 Leti researcher Sylvain Maitrejean described how with this technique he was able to boost the short-channel electron mobility by more than 20% compared with an unstrained reference—showing significant promise for enhancing the on-state currents of CMOS transistors and thus for improving the circuit’s speed.
The second technique is similar to strain-memorization methods and relies on the capability of the buried-oxide (BOX) layer to creep under high-temperature annealing.
At last year’s International Conference on Solid State Devices and Materials (SSDM 2015) in Sapporo, Japan, Leti researchers showed that with this local-stress technique they can turn regular unstrained SOI structures into tensile strained Si (sSOI) for NFET areas. Figure 1 shows a stress profile from 2D Raman extractions for Si MESAs after the “BOX-creep” process with 50-nm thick SiN. The researchers reported that this BOX-creep process also can be applied to compressive strain creation, as they described at the Silicon Nanoelectronics Workshop conference June 14-15 in Kyoto, Japan.
Figure 1. Stress profile after the BOX creep process as presented at SSDM 2015
Courtesy of CEA-Leti
“Leti has continuously focused on improving and fine-tuning FD-SOI technology’s inherent advantages since pioneering the technology 20 years ago,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory, in a press release. “These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices and further position the technology to be a vital part of the Internet of Things and electronics products of the future.”
And finally, Leti announced it has signed an agreement with Keysight Technologies to adapt Leti’s UTSOI extraction flow methodology within Keysight’s device-modeling solutions for high-volume SPICE model generation. The simulation of the Leti-UTSOI compact model currently is available in Keysight’s modeling and simulation tools. This agreement expands the collaboration to include the extraction flow and will enable device-modeling engineers to efficiently create Leti-UTSOI model cards for use in Process Design Kits.
“This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which already are available in all the major SPICE simulators,” said Marie Semeria, Leti’s CEO, in a press release. “This professional, automatic extraction-flow solution will address designers’ needs as they weigh FD-SOI’s benefits over competing solutions for the 28-nm technology node and below.”
“Keysight’s modeling solutions provide both automation and flexibility for device modeling,” added Todd Cutler, general manager of Keysight EEsof EDA. “The addition of a Leti-UTSOI modeling technology will further expand our offering in CMOS modeling. We have been collaborating with Leti on many projects, and we are pleased to extend our relationship to improve access to the Leti-UTSOI.”
Looking beyond silicon at IEDM was nanoelectronics research center imec, which demonstrated what it called “record enhancement” of novel InGaAs gate-all-around (GAA) channel devices integrated on 300-mm silicon. The organization said it is exploring emerging tunnel devices based on optimization of the same III-V compound semiconductor.
imec said it had optimized both the channel epitaxy quality and the gate-channel passivation to realize III-V-on-Si GAA devices with a record peak transconductance at 0.5 V. In search of device technologies beyond FinFETs and GAA nanowires for sub-0.5-V operations, imec said it is investigating InGaAs tunnel-FETs (TFETs). It added that homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimization on device operations and pave the way to advanced logic devices based on III-V-on-Si for high-performance or ultra-low power applications.
Specifically, imec presented GAA InGaAs nanowire FETs (gate length Lg = 50 nm) that performed at an average peak transconductance (gm) of 2200 µS/µm with a subthreshold swing of 110 mV/decade. imec succeeded in increasing the performance by gate-stack engineering using a novel gate stack atomic-layer-deposition (ALD) inter-layer (IL) material developed by ASM and high pressure annealing. The IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length of 50 nm, compared to the reference Al2O3/HfO2 stack.
imec also presented a planar InGaAs homo-junction TFET with 70% indium (In) content. The increase of In content from 53% to 70% in an 8-nm channel was found to significantly boost the performance of the device.
Deeply scaled CMOS
Also at IEDM, imec presented breakthrough results to increase performance and improve reliability of deeply scaled silicon CMOS logic devices.
Continued transistor scaling has resulted in increased transistor performance and transistor densities for the last 50 years, imec noted, adding that with transistor scaling reaching the critical limits of atomic dimensions, imec’s R&D program on advanced logic scaling targets the new and mounting challenges for performance, power, cost, and density scaling to future process technologies. The organization is looking into extending silicon CMOS technology by tackling the detrimental impact of parasitics on device performance and reliability and by introducing novel architectures such as GAA nanowires that are considered to improve short channel control.
Specific achievements reported at the meeting include a record low-contact resistivity of 1.5 Ωcm2 for n-Si, a decreased access resistance in NMOS Si bulk finFETs through the application of extension doping by phosphorus-doped silicate glass to achieve damage free and uniform sidewall doping of the fin, and junction-less high-k metal-gate-all-around nanowires to improve on- and off-state hot-carrier reliability.
In addition, imec presented three novel aluminum gallium nitride (AlGaN)/gallium nitride (GaN) stacks featuring optimized low dispersion buffer designs (Figure 2). Moreover, imec optimized the epitaxial p-GaN growth process on 200-mm silicon wafers, achieving e-mode devices featuring beyond state-of-the-art high threshold voltage and high drive current.
Courtesy of imec
To ensure a good current-collapse-free device operation in AlGaN/GaN-on-silicon devices, dispersion must be kept to a minimum, imec explained. Trapped charges in the buffer between the GaN-based channel and the silicon substrate are known to be a critical factor in causing dispersion. imec compared the impact of different types of buffers on dispersion and optimized three types: a classic step-graded buffer, a buffer with low-temperature AlN interlayers, and a super lattice buffer. These three types of buffers were optimized for low dispersion, leakage, and breakdown voltage over a wide temperature range and bias conditions.
imec also optimized the epitaxial p-GaN growth process demonstrating improved electrical performance of p-GaN HEMTs (high electron mobility transistors), achieving what it called a beyond state-of-the-art combination of high threshold voltage, low on-resistance, and high drive current. The p-GaN HEMT results outperformed their MIS-HEMT (metal-insulated semiconductor HEMT) counterparts.
imec’s GaN-on-Si R&D program aims at bringing this technology toward industrialization. imec’s offering includes a complete 200-mm CMOS-compatible 200-V GaN process line. imec’s program provides partners with early access to next-generation devices and power electronics processes, equipment, and technologies to speed up innovation with shared costs. Current R&D focuses on improving the performance and reliability of imec’s e-mode devices while in parallel pushing the boundaries of the technology through innovation in substrate technology, higher levels of integration, and exploration of novel device architectures.
- Mourey, B., “What chipmakers will need to address growing complexity, cost of IC design and yield ramps,” Solid State Technology, June 2015.
- Maitrejean, S., et al., “Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration,” ECS Journal of Solid State Science and Technology, pp. 376-381, volume 4, issue 9, 2015.