Synopsys addresses automotive, 7-nm IC test at ITC

Nov. 16, 2016

Fort Worth, TX. Synopsys is presenting news on a variety of fronts at the International Test Conference here this week. The company said that Imagination Technologies is leveraging Synopsys’ DesignWare STAR Memory System for memory built-in self-test (BIST) and repair of its new MIPS I6500 processor. The company also announced that leading automotive semiconductor suppliers are deploying its IC test solution for higher levels of quality, reliability, and functional safety. Looking toward the future, Synopsys announced it is expanding its test and yield analysis solution targeting FinFET-specific defects to enable higher quality testing, repair, diagnostics, and yield analysis of advanced 7-nm SoCs.

In addition, Robert Ruiz, director of product marketing for test automation at Synopsys, provided an update on TetraMAX II ATPG, introduced earlier this year. He said customers including Toshiba, ST, and Broadcom have been deploying the product. Toshiba, he said, reported that it had reduced pattern count by 50 to 90% and achieved speed increases of 2 to 13X. For automotive applications, Ruiz said, TetraMAX II ATPG is ISO 26262-certified for automotive safety integrity level ASIL D.

In addition to TetraMAX II ATPG, the full Synopsys ISO 26262-certified automotive test solution comprises SpyGlass DFT ADV for testability and soft-error analysis; Z01X high-performance fault simulation; DFTMAX LogicBIST and DesignWare STAR Memory System for in-system test as well as embedded test, repair, and diagnostics; DFTMAX Ultra for pin-limited compression; and DesignWare STAR Hierarchical System for automated hierarchical test of IP and logic blocks on an SoC.

Ruiz said issues addressed by the tools include soft errors for logic. He noted that functional fault simulation has never gone away, and the Z01X tool finds heavy use in automotive designs to reduce DPPM. In addition, cell-aware fault support provides an understanding of defect coverage within cells, and Synopsys tools provide consistent reporting of cell-aware coverage across functional and ATPG patterns.

The Z01X fault-simulation solution employs multithreading technology to accelerate fault simulation of functional test patterns, allowing designers of automotive ICs to increase test coverage by supplementing standard manufacturing tests with user-created functional patterns.

Ruiz also cited physically aware test-point insertion using the DFTMAX design-for-test solution in conjunction with SpyGlass DFT ADV RTL testability analysis. The tools support both placement-based and timing-based insertion. Test points increase fault coverage while decreasing pattern count.

The DesignWare STAR Hierarchical System incorporates new process and clock monitoring functionality to enhance IC reliability, Ruiz said, providing the ability to measure internal clock frequency and duty cycle without the need for an additional, higher frequency clock.

Commenting on 7-nm test readiness, Ruiz said Synopsys has expanded its test and yield analysis solution targeting FinFET-specific defects to enable higher quality testing, repair, diagnostics, and yield analysis. He said the tools include slack-based cell-aware technology to boost defect coverage and improve diagnostics. Cell-aware capability, he said, targets defects inside library cells based on HSPICE simulated injected faults, while cell-aware diagnostics reduces the time needed to find defects in cells by reducing the defect search area.

Ruiz said Synopsys is working on both 7-nm logic and memory. Synopsys manufactures memory test chips and correlates fault models to defects prevailing at every process node. He added that Synopsys is currently in collaboration with customers on 7-nm yield analysis.

Automotive chipmakers

Synopsys said its test solution is enabling semiconductor suppliers including Elmos Semiconductor, MegaChips, Micronas, Renesas Electronics, and Toshiba to meet automotive test goals in less time and at lower cost for millions of shipped ICs.

“Automotive semiconductor companies are successfully deploying Synopsys’ ISO 26262–certified test solution to meet their functional safety and quality goals,” said Bijan Kiani, vice president of marketing for the Synopsys Design Group, in a press release. “Synopsys has now expanded the solution to provide our customers even faster and more cost-effective means to attain the higher quality, reliability and safety requirements demanded by their customers.”

Synopsys said customers across the automotive supply chain use Synopsys Silicon to Software solutions to develop ICs and software for infotainment, ADAS, V2X, and autonomous driving applications. Synopsys said its portfolio of automotive-specific IC design tools, automotive-grade IP, and automotive software cybersecurity and quality solutions accelerate time to market and enable the next generation of safe, secure and smarter connected cars. For more visit http://www.synopsys.com/automotive.

Test and yield analysis at 7 nm

Regarding the 7-nm test-readiness announcement, Synopsys said its collaboration with customers is enabling rapid deployment of new functionality within Synopsys’ synthesis-based test solution, including TetraMAX II ATPG, DesignWare STAR Memory System, and DesignWare STAR Hierarchical System.

“The growing complexity and process variation found with advanced 7-nm FinFET processes requires improved test and yield technologies,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys, in a press release. “Our IP design teams are leveraging TetraMAX ATPG as well as STAR Memory System and STAR Hierarchical System test, repair and diagnostic solutions to help multiple customers designing with 7-nm IP improve their product quality and yield, while accelerating their time to market.”

“As a leading provider of comprehensive test and yield solutions, Synopsys is committed to helping designers meet their growing challenges of higher quality and faster yield ramp,” added Kiani. “Through our on-going collaborations with leading semiconductor companies worldwide, we are delivering innovative solutions to address the specific requirements for advanced FinFET processes. These innovations will enable our customers to rapidly adopt 7-nm technologies to meet their goals for high-performance SoC products.”

Imagination Technologies

And finally, Synopsys announced that Imagination Technologies is leveraging Synopsys’ DesignWare STAR Memory System for memory BIST and repair of its new MIPS I6500 processor. The DesignWare STAR Memory System’s multi-memory bus (MMB) processor provides common test and repair logic for all memory instances mapped to a shared bus, minimizing BIST impact on CPU performance and area. In addition, the MMB processor in the DesignWare STAR Memory System offers the flexibility to either decouple test logic from the block under test or optimally place the test logic within the block to reduce total die size while maintaining performance.

The MMB processor in the DesignWare STAR Memory System provides the automation and logic needed to quickly implement a comprehensive test and repair strategy for memory instances mapped on a test bus within a CPU-based system-on-chip (SoC). Using the MMB processor, designers can perform high-speed diagnostics, column or/and row repair, and soft or hard repair, and they can test specific memory sub-groups. The MMB processor is suited for high-performance design blocks and processor subsystems with L1, L2, or L3 caches optimized for maximum performance and minimal area.

“Synopsys and Imagination share a common goal of enabling designers to create high-performance SoCs,” said Jim Nicholas, executive vice president, MIPS Business Unit at Imagination, in a press release. “As an IP provider to many silicon design companies, it is important for Imagination to collaborate with industry partners to optimize the implementation of our licensable CPU cores. Using the DesignWare STAR Memory System with MMB processor for our new MIPS I6500 processor can significantly reduce the processors’ memory BIST area and accelerate CPU memory test integration effort while meeting our customers’ performance goals.”

“As the amount of cache memory in high-performance CPUs and GPUs increases, minimizing memory BIST impact on the functional path is critical,” added Koeter. “By using the MMB processor in the proven DesignWare STAR Memory System, designers can reduce their on-die test footprint without sacrificing performance and product quality goals. This announcement expands our relationship with Imagination in support of its advanced processor IP cores, including the high-performance MIPS I6500.”

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!