Fort Worth, TX. Mentor Graphics at the International Test Conference highlighted its new Tessent DefectSim product, which measures the defect coverage of any test applied to an analog or mixed-signal circuit. The company also highlighted its Tessent SiliconInsight product—an automated interactive environment for test bring-up, debug, and silicon characterization.
DefectSim can improve the quality and reliability of analog and mixed-signal circuits through the selection of more effective tests. Further, it can reduce the cost of test by showing which tests do not increase coverage. Tessent DefectSim satisfies the growing defect-coverage measurement requirement for automotive ICs set by Tier 1 automotive suppliers, according to Steve Pateras, product marketing director at Mentor Graphics.
“We’re seeing a need for analog test automation from a growing portion of our customer base,” Pateras said. “The automotive market has quickly expanded this need, making the unique automation provided by Tessent DefectSim a timely and valuable addition to our Tessent suite of test tools.” He called DefectSim the first step toward full analog test automation.
Tessent DefectSim works with Mentor’s Eldo and Questa ADMS circuit simulators to measure the effects of opens, shorts, extreme variations, and user-defined defects modeled within a layout-extracted or schematic netlist. A number of techniques reduce total simulation time by orders of magnitude, compared with sequential simulation of every defect in a flat layout-extracted netlist, without reducing simulation accuracy or limiting the type of test. Among the techniques is a new statistical method called likelihood-weighted random sampling, which minimizes the number of defects to simulate and more accurately indicates outgoing chip quality.
“In mixed-signal automotive ICs, about 80% of the defects found in returned ICs are in the analog circuitry,” said Wim Dobbelaere, director of test and product engineering at ON Semiconductor, in a press release. “The quality of analog circuitry is traditionally guaranteed using functional tests while the fault coverage remains unknown. A few years ago, we identified several ways to improve defect coverage of analog tests but the main gap towards improvement was the absence of an automated fault simulation tool. We had an extensive collaboration with Mentor during the development of Tessent DefectSim. We evaluated the tool on several automotive ICs and concluded it is a highly-automated and flexible solution that guides improvements in test and design-for-test techniques and allows us to measurably improve the defect coverage of analog tests.”
“We used DefectSim to investigate a simpler, faster structural test for an analog circuit that we manufacture,” added Peter Sarson, test development manager at the ams AG Full Service Foundry. “DefectSim showed us that the new test has defect coverage equal to that of our specification-based test, and now we only need to validate the new test in production. This tool paid for itself in one project.”
Tessent DefectSim can also measure a circuit’s tolerance to defects. Defect tolerance is a measure of a circuit’s ability, in the presence of defects, to either continue to operate within acceptable operational limits or to transition into a safe state. This metric is very important in automotive applications as it directly relates to long term reliability.
Mentor at ITC also highlighted its Tessent SiliconInsight product. Geir Eide, product marketing director, described it as an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent BIST or Tessent IJTAG test structures.
To use the tool, Eide said, you need a device and a performance board controlled by a laptop via a USB cable and JTAG interface card. The demo afforded the software company to bring hardware to ITC in the form of a sample performance board.
The Tessent SiliconInsight tool can complement other desktop debug tools.
In a video on Mentor’s site, Pateras demonstrates the software, a performance board, and an external clock generator and power supply that can exercise the device under test and determine under what clock speeds and power-supply levels a device might begin to fail.
He begins with a memory demonstration how memory is performing and how to improve it. “We are doing detailed performance characterization of one memory deep within the device on the desktop,” he says.
For logic, the tool can tell you what specific flip-flops are failing in response to what patterns at varying clock frequencies. You can tweak your design by changing the paths leading those flip-flops to improve the entire design through the desktop environment.
