Shrinking packages if not transistors

March 20, 2017
Rick Nelson,
Executive Editor

Moore’s Law faces increasing challenges as the ability to shrink transistors encounters physical and economic limits. In fact, last summer the Semiconductor Industry Association released the last International Technology Roadmap for Semiconductors (albeit it does look 15 years ahead). “For a quarter-century, the roadmap has been an important guidepost for evaluating and advancing semiconductor innovation,” said John Neuffer, SIA president and CEO, at the time of the release. “The latest and final installment provides key findings about the future of semiconductor technology and serves as a useful bridge to the next wave of semiconductor research initiatives.”
If it’s becoming impractical to shrink the transistors, perhaps an alternative research initiative would be to address shrinking the packages they go into. Following this line of reasoning, efforts are underway to continue driving the semiconductor industry forward.

One such initiative is the Heterogeneous Integration Roadmap, sponsored by organizations including the IEEE Components, Packaging, and Manufacturing Technology Society and SEMI. A technical session at the International Test Conference last fall addressed the topic, as I noted in my editorial in January.

Also last fall, the MicroElectronics Packaging and Test Engineering Council (MEPTEC) addressed the topic at its 2016 Semiconductor Packaging Roadmap Symposium, at which MEPTEC said it was initiating collaboration with Heterogeneous Integration Roadmap supporters. Among the symposium participants, Smoltek, an 11-year-old startup that spun out of Chalmers University, represented nanotechnology as what it called “a substantial option” for the future of semiconductors.

“The bottom line is that there is a strong need for a technological shift from the trend of scaling the transistors to the reduction of the size of an electronic package,” according to a Smoltek white paper. In pursuit of package-size reduction, the company specializes in the development of nanostructure fabrication technology to solve advanced materials engineering problems for advanced semiconductor packaging applications.

Specifically, Smoltek’s Tiger carbon-nanostructure-based assembly platform supports stacking bare dies on each other or bonding them to a substrate (interposer) or carrier (lead frame) using arrays of nanostructure-enabled metallic pillars. The technology enables the integration of components including standard ICs, ASICs, FPGAs, memories, and microcontrollers as well as the embedding of additional functionality such as energy storage in the form of solid-state supercapacitors. The platform, the company estimates, offers tenfold to a hundredfold 3D shrinkage compared with established bump-and-pillar technologies.

In a recent phone interview, Anders Johansson, CEO of Smoltek, described the MEPTEC symposium as one of many such events in which his company participates. He cited the symposium’s “interesting focus on the heterogeneous field where we see our technology fitting so well”—particularly with regard to integrating several die into one advanced package, as in SiP technology. He said the company has demonstrated integrated capacitors on an interposer, thermal interface materials, and microbumps. A key achievement for the company has been to reduce the growth temperature for the conductive carbon nanostructures to below 390°C, making the technology compatible with CMOS processes.

Johansson said he has spent more than six years at Smoltek working on commercialization of the technology, which is protected by patents, including a European patent granted in February. He said he has seen a significant increase in interest in the technology over the last year and a half. The company’s goal is to license its IP and support the integration of its processes. “We have clear ambition to have our first license agreement signed this year,” he said.

Whatever the outcome of specific commercial platforms and organizational initiatives, it’s encouraging to see companies and organizations supplant the guidance toward the semiconductor industry’s future once provided by the ITRS.

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