Sunnyvale, CA. Rambus Inc. today announced it is collaborating with PLDA, a provider of PCI Express controller IP solutions, and Avery Design Systems Inc., an innovator in functional verification productivity solutions, to offer a comprehensive, silicon-proven PCI Express (PCIe) 4.0 solution, with backward compatibility to PCIe 3.0 and 2.0. The new PCIe subsystem includes a Rambus SerDes PHY, a PLDA PCIe controller, and Avery Design’s verification IP. The solution is pre-verified and validated for simple integration into ASICs.
“Our collaboration with PLDA and Avery Design offers customers a complete, pre-verified PCIe subsystem, with silicon-proven SerDes and a PCIe controller,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “Our line-up of SerDes PHYs is optimized for power and efficiency, delivering maximum performance and flexibility for today’s most challenging systems for a variety of applications including networking, data center, and high-performance computing.”
“Our new solution enables designers to quickly bring their products to market using a subsystem that combines the expertise of proven industry leaders, including Rambus, for their broad portfolio of PHYs, and Avery, for their comprehensive verification solutions,” said Arnaud Schleich, CEO at PLDA. “This platform, which supports endpoint, root port, and switch applications, demonstrates the high quality of our PCI Express IP cores, solving performance and integration issues in the market.”
“We are excited to team with PLDA and Rambus to offer designers a complete, pre-validated sub-system solution to get their PCIe solution to market,” said Chris Browy, vice president of sales and marketing at Avery Design. “Pre-qualifying the new PCIe solution with Avery’s VIP solutions enables customers to reduce verification cycles and implementation risks for their PCI Express solution.”
